| Line 227... |
Line 227... |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
$fdisplay(fexe, "ESR0 : %h", r);
|
$fdisplay(fexe, "ESR0 : %h", r);
|
insns = insns + 1;
|
insns = insns + 1;
|
`endif
|
`endif
|
end
|
end
|
endtask
|
endtask // display_arch_state
|
|
|
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
|
* an instruction that is invalid, such as all zeros.
|
|
* Currently, only breaks on an all zero instruction, but should probably be
|
|
* made to break for anything with an X in it too. And of course ideally this
|
|
* shouldn't be needed - but is handy if someone changes something and stops
|
|
* the test continuing forever.
|
|
*/
|
|
task monitor_for_crash;
|
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
|
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
|
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
|
|
integer i;
|
|
|
|
begin
|
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
|
|
begin
|
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
|
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
|
|
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
|
end
|
|
#100 $finish;
|
|
end
|
|
else
|
|
begin
|
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
|
insn_trace[i] = insn_trace[i-1];
|
|
addr_trace[i] = addr_trace[i-1];
|
|
end
|
|
insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
|
|
addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
|
|
end
|
|
|
|
end
|
|
endtask // monitor_for_crash
|
|
|
|
|
//
|
//
|
// Write state of the OR1200 registers into a file; version for exception
|
// Write state of the OR1200 registers into a file; version for exception
|
//
|
//
|
task display_arch_state_except;
|
task display_arch_state_except;
|
| Line 362... |
Line 402... |
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
|
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
|
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
|
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
|
#2;
|
#2;
|
if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
|
if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
|
&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
|
&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
|
|
begin
|
display_arch_state;
|
display_arch_state;
|
|
monitor_for_crash;
|
|
end
|
else
|
else
|
if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
|
if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
|
display_arch_state_except;
|
display_arch_state_except;
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
