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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 26 and 30

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Rev 26 Rev 30
Line 205... Line 205... 
initial
 
initial
 
  begin
 
  begin
 
     $display("\nStarting RTL simulation of %s test\n", "`TEST_NAME_STRING");
 
     $display("\nStarting RTL simulation of %s test\n", "`TEST_NAME_STRING");
 
  end
 
  end
 
 
 
 
 
`ifdef VCD
 
 
 
 
 
`ifdef LXT
 
   initial
 
   initial
 
     begin
 
     begin
 
        $display("VCD in %s\n", {"`TEST_NAME_STRING",".vcd"});
 
        $display("LXT (optimized VCD) dumpfile: %s\n", {`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".vcd"});
 
        $dumpfile({"`TEST_NAME_STRING",".vcd"});
 
        $dumpfile({`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".lxt"});
 
        $dumpvars(0);
 
        $dumpvars(0);
 
     end
 
     end
 
`endif
 
`endif
 
 
 
 
 
endmodule // orpsoc_testbench
 
endmodule // orpsoc_testbench

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