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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 30 and 31

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Rev 30 Rev 31
Line 206... Line 206...
  begin
  begin
     $display("\nStarting RTL simulation of %s test\n", "`TEST_NAME_STRING");
     $display("\nStarting RTL simulation of %s test\n", "`TEST_NAME_STRING");
  end
  end
 
 
 
 
`ifdef LXT
`ifdef VCD
   initial
   initial
     begin
     begin
        $display("LXT (optimized VCD) dumpfile: %s\n", {`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".vcd"});
        $display("VCD in %s\n", {`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".vcd"});
        $dumpfile({`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".lxt"});
        $dumpfile({`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".vcd"});
        $dumpvars(0);
        $dumpvars(0);
     end
     end
`endif
`endif
 
 
endmodule // orpsoc_testbench
endmodule // orpsoc_testbench

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