URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 32 and 34

Rev 32	Rev 34
Line 199...	Line 199...
`.Ras_n (mem_ras_o),`	`.Ras_n (mem_ras_o),`
`.Cas_n (mem_cas_o),`	`.Cas_n (mem_cas_o),`
`.We_n (mem_we_o),`	`.We_n (mem_we_o),`
`.Dqm (mem_dqm_o));`	`.Dqm (mem_dqm_o));`


`initial`	`initial`
`begin`	`begin`
$display("\nStarting RTL simulation of %s test\n", "`TEST_NAME_STRING");	$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
`end`


`ifdef VCD	`ifdef VCD
`initial`	$display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
`begin`	$dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
$display("VCD in %s\n", {`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".vcd"});
$dumpfile({`TESTBENCH_RESULTS_DIR,"`TEST_NAME_STRING",".vcd"});
`$dumpvars(0);`	`$dumpvars(0);`
`end`
`endif	`endif
	`end`


`endmodule // orpsoc_testbench`	`endmodule // orpsoc_testbench`

`// Local Variables:`	`// Local Variables:`
`// verilog-library-files:("../../rtl/verilog/orp_soc.v")`	`// verilog-library-files:("../../rtl/verilog/orp_soc.v")`