URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 43 and 45

Rev 43	Rev 45
Line 169...	Line 169...
`.dbg_tck_pad_i (dbg_tck_i),`	`.dbg_tck_pad_i (dbg_tck_i),`
`.dbg_tms_pad_i (dbg_tms_i),`	`.dbg_tms_pad_i (dbg_tms_i),`
`.rst_pad_i (rst_i),`	`.rst_pad_i (rst_i),`
`.clk_pad_i (clk_i));`	`.clk_pad_i (clk_i));`

	`ifdef USE_SDRAM
`// SPI Flash`	`// SPI Flash`
`AT26DFxxx spi_flash`	`AT26DFxxx spi_flash`
`(`	`(`
`// Outputs`	`// Outputs`
`.SO (spi_flash_miso_i),`	`.SO (spi_flash_miso_i),`
Line 199...	Line 199...
`.Ras_n (mem_ras_o),`	`.Ras_n (mem_ras_o),`
`.Cas_n (mem_cas_o),`	`.Cas_n (mem_cas_o),`
`.We_n (mem_we_o),`	`.We_n (mem_we_o),`
`.Dqm (mem_dqm_o));`	`.Dqm (mem_dqm_o));`

	`else // !`ifdef USE_SDRAM
	`assign spi_flash_miso_i = 1'b0; // Tie off master-in/slave-out SPI signal`
	`assign mem_dat_io = 16'hzzzz; // Hi-Z the SDRAM bus`
	`endif // !`ifdef USE_SDRAM


`initial`	`initial`
`begin`	`begin`
$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);	$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
`ifdef VCD	`ifdef VCD
$display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});	$display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});