| Line 69... |
Line 69... |
rst <= 1;
|
rst <= 1;
|
end
|
end
|
|
|
|
|
// Wires for the dut
|
// Wires for the dut
|
wire spi_flash_sclk_o;
|
|
wire spi_flash_ss_o;
|
|
wire spi_flash_miso_i;
|
|
wire spi_flash_mosi_o;
|
|
wire spi_flash_w_n_o;
|
|
wire spi_flash_hold_n_o;
|
|
wire spi_sd_sclk_o;
|
wire spi_sd_sclk_o;
|
wire spi_sd_ss_o;
|
wire spi_sd_ss_o;
|
wire spi_sd_miso_i;
|
wire spi_sd_miso_i;
|
wire spi_sd_mosi_o;
|
wire spi_sd_mosi_o;
|
|
`ifdef USE_SDRAM
|
wire [15:0] mem_dat_io;
|
wire [15:0] mem_dat_io;
|
wire [12:0] mem_adr_o;
|
wire [12:0] mem_adr_o;
|
wire [1:0] mem_dqm_o;
|
wire [1:0] mem_dqm_o;
|
wire [1:0] mem_ba_o;
|
wire [1:0] mem_ba_o;
|
wire mem_cs_o;
|
wire mem_cs_o;
|
wire mem_ras_o;
|
wire mem_ras_o;
|
wire mem_cas_o;
|
wire mem_cas_o;
|
wire mem_we_o;
|
wire mem_we_o;
|
wire mem_cke_o;
|
wire mem_cke_o;
|
|
wire spi_flash_sclk_o;
|
|
wire spi_flash_ss_o;
|
|
wire spi_flash_miso_i;
|
|
wire spi_flash_mosi_o;
|
|
wire spi_flash_w_n_o;
|
|
wire spi_flash_hold_n_o;
|
|
`endif // `ifdef USE_SDRAM
|
|
|
|
`ifdef USE_ETHERNET
|
wire [1:1] eth_sync_o;
|
wire [1:1] eth_sync_o;
|
wire [1:1] eth_tx_o;
|
wire [1:1] eth_tx_o;
|
wire [1:1] eth_rx_i;
|
wire [1:1] eth_rx_i;
|
wire eth_clk_i;
|
wire eth_clk_i;
|
wire [1:1] eth_md_io;
|
wire [1:1] eth_md_io;
|
wire [1:1] eth_mdc_o;
|
wire [1:1] eth_mdc_o;
|
|
`endif
|
|
|
wire spi1_mosi_o;
|
wire spi1_mosi_o;
|
wire spi1_miso_i;
|
wire spi1_miso_i;
|
|
|
wire spi1_ss_o;
|
wire spi1_ss_o;
|
wire spi1_sclk_o;
|
wire spi1_sclk_o;
|
wire [8-1:0] gpio_a_io;
|
wire [8-1:0] gpio_a_io;
|
wire uart0_srx_i;
|
wire uart0_srx_i;
|
wire uart0_stx_o;
|
wire uart0_stx_o;
|
| Line 115... |
Line 120... |
|
|
assign clk_i = clk;
|
assign clk_i = clk;
|
assign rst_i = rst;
|
assign rst_i = rst;
|
|
|
// Tie off some inputs
|
// Tie off some inputs
|
assign eth_rx_i = 0;
|
|
assign eth_clk_i = 0;
|
|
assign spi1_miso_i = 0;
|
assign spi1_miso_i = 0;
|
assign uart0_srx_i = 1;
|
assign uart0_srx_i = 1;
|
assign dbg_tdi_i = 1;
|
assign dbg_tdi_i = 1;
|
assign dbg_tck_i = 0;
|
assign dbg_tck_i = 0;
|
assign dbg_tms_i = 1;
|
assign dbg_tms_i = 1;
|
|
|
|
|
orpsoc_top dut
|
orpsoc_top dut
|
(
|
(
|
// Outputs
|
// Outputs
|
.spi_flash_sclk_pad_o (spi_flash_sclk_o),
|
|
.spi_flash_ss_pad_o (spi_flash_ss_o),
|
|
.spi_flash_mosi_pad_o (spi_flash_mosi_o),
|
|
.spi_flash_w_n_pad_o (spi_flash_w_n_o),
|
|
.spi_flash_hold_n_pad_o (spi_flash_hold_n_o),
|
|
.spi_sd_sclk_pad_o (spi_sd_sclk_o),
|
.spi_sd_sclk_pad_o (spi_sd_sclk_o),
|
.spi_sd_ss_pad_o (spi_sd_ss_o),
|
.spi_sd_ss_pad_o (spi_sd_ss_o),
|
.spi_sd_mosi_pad_o (spi_sd_mosi_o),
|
.spi_sd_mosi_pad_o (spi_sd_mosi_o),
|
.mem_adr_pad_o (mem_adr_o[12:0]),
|
|
.mem_dqm_pad_o (mem_dqm_o[1:0]),
|
|
.mem_ba_pad_o (mem_ba_o[1:0]),
|
|
.mem_cs_pad_o (mem_cs_o),
|
|
.mem_ras_pad_o (mem_ras_o),
|
|
.mem_cas_pad_o (mem_cas_o),
|
|
.mem_we_pad_o (mem_we_o),
|
|
.mem_cke_pad_o (mem_cke_o),
|
|
.eth_sync_pad_o (eth_sync_o[1:1]),
|
|
.eth_tx_pad_o (eth_tx_o[1:1]),
|
|
.eth_mdc_pad_o (eth_mdc_o[1:1]),
|
|
.spi1_mosi_pad_o (spi1_mosi_o),
|
.spi1_mosi_pad_o (spi1_mosi_o),
|
.spi1_ss_pad_o (spi1_ss_o),
|
.spi1_ss_pad_o (spi1_ss_o),
|
.spi1_sclk_pad_o (spi1_sclk_o),
|
.spi1_sclk_pad_o (spi1_sclk_o),
|
.uart0_stx_pad_o (uart0_stx_o),
|
.uart0_stx_pad_o (uart0_stx_o),
|
.dbg_tdo_pad_o (dbg_tdo_o),
|
.dbg_tdo_pad_o (dbg_tdo_o),
|
.rst_pad_o (rst_o),
|
.rst_pad_o (rst_o),
|
// Inouts
|
|
.mem_dat_pad_io (mem_dat_io[15:0]),
|
|
.eth_md_pad_io (eth_md_io[1:1]),
|
|
.gpio_a_pad_io (gpio_a_io[8-1:0]),
|
.gpio_a_pad_io (gpio_a_io[8-1:0]),
|
// Inputs
|
// Inputs
|
.spi_flash_miso_pad_i (spi_flash_miso_i),
|
|
.spi_sd_miso_pad_i (spi_sd_miso_i),
|
.spi_sd_miso_pad_i (spi_sd_miso_i),
|
.eth_rx_pad_i (eth_rx_i[1:1]),
|
|
.eth_clk_pad_i (eth_clk_i),
|
|
.spi1_miso_pad_i (spi1_miso_i),
|
.spi1_miso_pad_i (spi1_miso_i),
|
.uart0_srx_pad_i (uart0_srx_i),
|
.uart0_srx_pad_i (uart0_srx_i),
|
.dbg_tdi_pad_i (dbg_tdi_i),
|
.dbg_tdi_pad_i (dbg_tdi_i),
|
.dbg_tck_pad_i (dbg_tck_i),
|
.dbg_tck_pad_i (dbg_tck_i),
|
.dbg_tms_pad_i (dbg_tms_i),
|
.dbg_tms_pad_i (dbg_tms_i),
|
|
`ifdef USE_ETHERNET
|
|
// Ethernet ports
|
|
.eth_md_pad_io (eth_md_io[1:1]),
|
|
.eth_sync_pad_o (eth_sync_o[1:1]),
|
|
.eth_tx_pad_o (eth_tx_o[1:1]),
|
|
.eth_mdc_pad_o (eth_mdc_o[1:1]),
|
|
.eth_rx_pad_i (eth_rx_i[1:1]),
|
|
.eth_clk_pad_i (eth_clk_i),
|
|
`endif // `ifdef USE_ETHERNET
|
|
// SDRAM and flash memory ports
|
|
`ifdef USE_SDRAM
|
|
.mem_dat_pad_io (mem_dat_io[15:0]),
|
|
.mem_adr_pad_o (mem_adr_o[12:0]),
|
|
.mem_dqm_pad_o (mem_dqm_o[1:0]),
|
|
.mem_ba_pad_o (mem_ba_o[1:0]),
|
|
.mem_cs_pad_o (mem_cs_o),
|
|
.mem_ras_pad_o (mem_ras_o),
|
|
.mem_cas_pad_o (mem_cas_o),
|
|
.mem_we_pad_o (mem_we_o),
|
|
.mem_cke_pad_o (mem_cke_o),
|
|
.spi_flash_sclk_pad_o (spi_flash_sclk_o),
|
|
.spi_flash_ss_pad_o (spi_flash_ss_o),
|
|
.spi_flash_mosi_pad_o (spi_flash_mosi_o),
|
|
.spi_flash_w_n_pad_o (spi_flash_w_n_o),
|
|
.spi_flash_hold_n_pad_o (spi_flash_hold_n_o),
|
|
.spi_flash_miso_pad_i (spi_flash_miso_i),
|
|
`endif
|
.rst_pad_i (rst_i),
|
.rst_pad_i (rst_i),
|
.clk_pad_i (clk_i));
|
.clk_pad_i (clk_i));
|
|
|
|
// External memories, if enabled
|
`ifdef USE_SDRAM
|
`ifdef USE_SDRAM
|
// SPI Flash
|
// SPI Flash
|
AT26DFxxx spi_flash
|
AT26DFxxx spi_flash
|
(
|
(
|
// Outputs
|
// Outputs
|
| Line 199... |
Line 208... |
.Ras_n (mem_ras_o),
|
.Ras_n (mem_ras_o),
|
.Cas_n (mem_cas_o),
|
.Cas_n (mem_cas_o),
|
.We_n (mem_we_o),
|
.We_n (mem_we_o),
|
.Dqm (mem_dqm_o));
|
.Dqm (mem_dqm_o));
|
|
|
`else // !`ifdef USE_SDRAM
|
|
assign spi_flash_miso_i = 1'b0; // Tie off master-in/slave-out SPI signal
|
|
assign mem_dat_io = 16'hzzzz; // Hi-Z the SDRAM bus
|
|
`endif // !`ifdef USE_SDRAM
|
`endif // !`ifdef USE_SDRAM
|
|
|
|
|
initial
|
initial
|
begin
|
begin
|
$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
|
$display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
|
|
`ifdef USE_SDRAM
|
|
$display("Using SDRAM - loading application from SPI flash memory\n");
|
|
`endif
|
|
|
`ifdef VCD
|
`ifdef VCD
|
$display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
|
$display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
|
$dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
|
$dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
|
$dumpvars(0);
|
$dumpvars(0);
|
`endif
|
`endif
|
