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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ORPSoC Testbench file ////
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//// ORPSoC Testbench file ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - Determine a timeout for each test and load it by defines ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - jb, jb@orsoc.se ////
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//// - jb, jb@orsoc.se ////
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//// ////
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//// ////
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//// ////
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//// ////
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end
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end
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// Instantiate the monitor
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// Instantiate the monitor
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or1200_monitor monitor();
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or1200_monitor monitor();
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// If we're using UART for printf output, include the
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// UART decoder
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`ifdef UART_PRINTF
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// Define the UART's txt line for it to listen to
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`define UART_TX_LINE uart0_stx_o
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`define UART_BAUDRATE 115200
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`include "uart_decoder.v"
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`endif
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endmodule // orpsoc_testbench
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endmodule // orpsoc_testbench
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// Local Variables:
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// Local Variables:
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// verilog-library-files:("../../rtl/verilog/orp_soc.v")
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// verilog-library-files:("../../rtl/verilog/orp_soc.v")
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// verilog-library-directories:("." "../../rtl/verilog")
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// verilog-library-directories:("." "../../rtl/verilog")
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