URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [debug_if/] [dbg_top.v] - Diff between revs 18 and 43

Rev 18	Rev 43
Line 452...	Line 452...
`module_select <= #1 1'b1;`	`module_select <= #1 1'b1;`
`else if (update_dr_i)`	`else if (update_dr_i)`
`module_select <= #1 1'b0;`	`module_select <= #1 1'b0;`
`end`	`end`

	`/* verilator lint_off COMBDLY */`
`always @ (module_id)`	`always @ (module_id)`
`begin`	`begin`
`ifdef DBG_CPU0_SUPPORTED	`ifdef DBG_CPU0_SUPPORTED
`cpu0_debug_module <= #1 1'b0;`	`cpu0_debug_module <= #1 1'b0;`
`endif	`endif
Line 479...	Line 479...
`DBG_TOP_WISHBONE_DEBUG_MODULE : wishbone_module <= #1 1'b1;	`DBG_TOP_WISHBONE_DEBUG_MODULE : wishbone_module <= #1 1'b1;
`endif	`endif
`default : module_select_error <= #1 1'b1;`	`default : module_select_error <= #1 1'b1;`
`endcase`	`endcase`
`end`	`end`
	`/* verilator lint_on COMBDLY */`

`assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);`	`assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);`


`always @ (posedge tck_i or posedge rst_i)`	`always @ (posedge tck_i or posedge rst_i)`