| Line 148... |
Line 148... |
reg [31:0] m2_wb_dat_o;
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reg [31:0] m2_wb_dat_o;
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reg m1_wb_err_o;
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reg m1_wb_err_o;
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reg m2_wb_err_o;
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reg m2_wb_err_o;
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// Added to allow compilation with Verilator
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wire M1_ADDRESSED_S1_wire;
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assign M1_ADDRESSED_S1_wire = `M1_ADDRESSED_S1;
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wire M1_ADDRESSED_S2_wire;
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assign M1_ADDRESSED_S2_wire = `M1_ADDRESSED_S2;
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wire M2_ADDRESSED_S1_wire;
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assign M2_ADDRESSED_S1_wire = `M2_ADDRESSED_S1;
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wire M2_ADDRESSED_S2_wire;
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assign M2_ADDRESSED_S2_wire = `M2_ADDRESSED_S2;
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wire m_wb_access_finished;
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wire m_wb_access_finished;
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (M1_ADDRESSED_S1_wire | M1_ADDRESSED_S2_wire);
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wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
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wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (M2_ADDRESSED_S1_wire | M2_ADDRESSED_S2_wire);
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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begin
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begin
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| Line 177... |
Line 188... |
begin
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begin
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case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
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case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
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5'b00_10_0, 5'b00_11_0 :
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5'b00_10_0, 5'b00_11_0 :
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begin
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begin
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m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
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m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
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if(`M1_ADDRESSED_S1)
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if(M1_ADDRESSED_S1_wire)
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begin
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begin
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s1_wb_adr_o <=#Tp m1_wb_adr_i;
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s1_wb_adr_o <=#Tp m1_wb_adr_i;
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s1_wb_sel_o <=#Tp m1_wb_sel_i;
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s1_wb_sel_o <=#Tp m1_wb_sel_i;
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s1_wb_we_o <=#Tp m1_wb_we_i;
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s1_wb_we_o <=#Tp m1_wb_we_i;
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s1_wb_dat_o <=#Tp m1_wb_dat_i;
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s1_wb_dat_o <=#Tp m1_wb_dat_i;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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end
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end
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else if(`M1_ADDRESSED_S2)
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else if(M1_ADDRESSED_S2_wire)
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begin
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begin
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s2_wb_adr_o <=#Tp m1_wb_adr_i;
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s2_wb_adr_o <=#Tp m1_wb_adr_i;
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s2_wb_sel_o <=#Tp m1_wb_sel_i;
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s2_wb_sel_o <=#Tp m1_wb_sel_i;
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s2_wb_we_o <=#Tp m1_wb_we_i;
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s2_wb_we_o <=#Tp m1_wb_we_i;
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s2_wb_dat_o <=#Tp m1_wb_dat_i;
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s2_wb_dat_o <=#Tp m1_wb_dat_i;
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| Line 201... |
Line 212... |
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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end
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end
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5'b00_01_0 :
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5'b00_01_0 :
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begin
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begin
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m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
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m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
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if(`M2_ADDRESSED_S1)
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if(M2_ADDRESSED_S1_wire)
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begin
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begin
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s1_wb_adr_o <=#Tp m2_wb_adr_i;
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s1_wb_adr_o <=#Tp m2_wb_adr_i;
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s1_wb_sel_o <=#Tp m2_wb_sel_i;
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s1_wb_sel_o <=#Tp m2_wb_sel_i;
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s1_wb_we_o <=#Tp m2_wb_we_i;
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s1_wb_we_o <=#Tp m2_wb_we_i;
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s1_wb_dat_o <=#Tp m2_wb_dat_i;
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s1_wb_dat_o <=#Tp m2_wb_dat_i;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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end
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end
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else if(`M2_ADDRESSED_S2)
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else if(M2_ADDRESSED_S2_wire)
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begin
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begin
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s2_wb_adr_o <=#Tp m2_wb_adr_i;
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s2_wb_adr_o <=#Tp m2_wb_adr_i;
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s2_wb_sel_o <=#Tp m2_wb_sel_i;
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s2_wb_sel_o <=#Tp m2_wb_sel_i;
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s2_wb_we_o <=#Tp m2_wb_we_i;
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s2_wb_we_o <=#Tp m2_wb_we_i;
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s2_wb_dat_o <=#Tp m2_wb_dat_i;
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s2_wb_dat_o <=#Tp m2_wb_dat_i;
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| Line 225... |
Line 236... |
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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end
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end
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5'b10_10_1, 5'b10_11_1 :
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5'b10_10_1, 5'b10_11_1 :
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begin
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begin
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m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
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m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
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if(`M1_ADDRESSED_S1)
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if(M1_ADDRESSED_S1_wire)
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begin
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begin
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s1_wb_cyc_o <=#Tp 1'b0;
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s1_wb_cyc_o <=#Tp 1'b0;
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s1_wb_stb_o <=#Tp 1'b0;
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s1_wb_stb_o <=#Tp 1'b0;
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end
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end
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else if(`M1_ADDRESSED_S2)
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else if(M1_ADDRESSED_S2_wire)
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begin
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begin
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s2_wb_cyc_o <=#Tp 1'b0;
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s2_wb_cyc_o <=#Tp 1'b0;
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s2_wb_stb_o <=#Tp 1'b0;
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s2_wb_stb_o <=#Tp 1'b0;
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end
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end
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end
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end
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5'b01_01_1, 5'b01_11_1 :
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5'b01_01_1, 5'b01_11_1 :
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begin
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begin
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m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
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m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
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if(`M2_ADDRESSED_S1)
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if(M2_ADDRESSED_S1_wire)
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begin
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begin
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s1_wb_cyc_o <=#Tp 1'b0;
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s1_wb_cyc_o <=#Tp 1'b0;
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s1_wb_stb_o <=#Tp 1'b0;
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s1_wb_stb_o <=#Tp 1'b0;
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end
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end
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else if(`M2_ADDRESSED_S2)
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else if(M2_ADDRESSED_S2_wire)
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begin
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begin
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s2_wb_cyc_o <=#Tp 1'b0;
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s2_wb_cyc_o <=#Tp 1'b0;
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s2_wb_stb_o <=#Tp 1'b0;
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s2_wb_stb_o <=#Tp 1'b0;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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// Generating Ack for master 1
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// Generating Ack for master 1
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always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
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always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M1_ADDRESSED_S1_wire or M1_ADDRESSED_S2_wire)
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begin
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begin
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if(m1_in_progress)
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if(m1_in_progress)
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begin
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begin
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if(`M1_ADDRESSED_S1) begin
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if(M1_ADDRESSED_S1_wire) begin
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m1_wb_ack_o <= s1_wb_ack_i;
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m1_wb_ack_o <= s1_wb_ack_i;
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m1_wb_dat_o <= s1_wb_dat_i;
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m1_wb_dat_o <= s1_wb_dat_i;
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end
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end
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else if(`M1_ADDRESSED_S2) begin
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else if(M1_ADDRESSED_S2_wire) begin
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m1_wb_ack_o <= s2_wb_ack_i;
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m1_wb_ack_o <= s2_wb_ack_i;
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m1_wb_dat_o <= s2_wb_dat_i;
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m1_wb_dat_o <= s2_wb_dat_i;
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end
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end
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end
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end
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else
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else
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m1_wb_ack_o <= 0;
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m1_wb_ack_o <= 0;
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end
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end
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// Generating Ack for master 2
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// Generating Ack for master 2
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always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
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always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire)
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begin
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begin
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if(m2_in_progress)
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if(m2_in_progress)
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begin
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begin
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if(`M2_ADDRESSED_S1) begin
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if(M2_ADDRESSED_S1_wire) begin
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m2_wb_ack_o <= s1_wb_ack_i;
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m2_wb_ack_o <= s1_wb_ack_i;
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m2_wb_dat_o <= s1_wb_dat_i;
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m2_wb_dat_o <= s1_wb_dat_i;
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end
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end
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else if(`M2_ADDRESSED_S2) begin
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else if(M2_ADDRESSED_S2_wire) begin
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m2_wb_ack_o <= s2_wb_ack_i;
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m2_wb_ack_o <= s2_wb_ack_i;
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m2_wb_dat_o <= s2_wb_dat_i;
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m2_wb_dat_o <= s2_wb_dat_i;
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end
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end
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end
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end
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else
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else
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m2_wb_ack_o <= 0;
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m2_wb_ack_o <= 0;
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end
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end
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// Generating Err for master 1
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// Generating Err for master 1
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always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
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always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or
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m1_wb_cyc_i or m1_wb_stb_i)
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m1_wb_cyc_i or m1_wb_stb_i)
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begin
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begin
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if(m1_in_progress) begin
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if(m1_in_progress) begin
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if(`M1_ADDRESSED_S1)
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if(M1_ADDRESSED_S1_wire)
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m1_wb_err_o <= s1_wb_err_i;
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m1_wb_err_o <= s1_wb_err_i;
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else if(`M1_ADDRESSED_S2)
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else if(M1_ADDRESSED_S2_wire)
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m1_wb_err_o <= s2_wb_err_i;
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m1_wb_err_o <= s2_wb_err_i;
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end
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end
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else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
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else if(m1_wb_cyc_i & m1_wb_stb_i & ~M1_ADDRESSED_S1_wire & ~M1_ADDRESSED_S2_wire)
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m1_wb_err_o <= 1'b1;
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m1_wb_err_o <= 1'b1;
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else
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else
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m1_wb_err_o <= 1'b0;
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m1_wb_err_o <= 1'b0;
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end
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end
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// Generating Err for master 2
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// Generating Err for master 2
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always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
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always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or
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m2_wb_cyc_i or m2_wb_stb_i)
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m2_wb_cyc_i or m2_wb_stb_i)
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begin
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begin
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if(m2_in_progress) begin
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if(m2_in_progress) begin
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if(`M2_ADDRESSED_S1)
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if(M2_ADDRESSED_S1_wire)
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m2_wb_err_o <= s1_wb_err_i;
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m2_wb_err_o <= s1_wb_err_i;
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else if(`M2_ADDRESSED_S2)
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else if(M2_ADDRESSED_S2_wire)
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m2_wb_err_o <= s2_wb_err_i;
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m2_wb_err_o <= s2_wb_err_i;
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end
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end
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else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
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else if(m2_wb_cyc_i & m2_wb_stb_i & ~M2_ADDRESSED_S1_wire & ~M2_ADDRESSED_S2_wire)
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m2_wb_err_o <= 1'b1;
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m2_wb_err_o <= 1'b1;
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else
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else
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m2_wb_err_o <= 1'b0;
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m2_wb_err_o <= 1'b0;
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end
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end
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