URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [ethernet/] [eth_registers.v] - Diff between revs 18 and 43

Rev 18	Rev 43
Line 826...	Line 826...
`.Clk (Clk),`	`.Clk (Clk),`
`.Reset (Reset)`	`.Reset (Reset)`
`);`	`);`
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;	assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;

	`/* verilator lint_off COMBDLY */`

`// Reading data from registers`	`// Reading data from registers`
`always @ (Address or Read or MODEROut or INT_SOURCEOut or`	`always @ (Address or Read or MODEROut or INT_SOURCEOut or`
`INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or`	`INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or`
`PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or`	`PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or`
Line 869...	Line 869...
`end`	`end`
`else`	`else`
`DataOut<=32'h0;`	`DataOut<=32'h0;`
`end`	`end`

	`/* verilator lint_on COMBDLY */`

`assign r_RecSmall = MODEROut[16];`	`assign r_RecSmall = MODEROut[16];`
`assign r_Pad = MODEROut[15];`	`assign r_Pad = MODEROut[15];`
`assign r_HugEn = MODEROut[14];`	`assign r_HugEn = MODEROut[14];`
`assign r_CrcEn = MODEROut[13];`	`assign r_CrcEn = MODEROut[13];`