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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1200r2/] [or1200_gmultp2_32x32.v] - Diff between revs 18 and 43

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Rev 18 Rev 43
Line 98... Line 98...
integer                   yi;
integer                   yi;
 
 
//
//
// Conversion unsigned to signed
// Conversion unsigned to signed
//
//
 
 /* verilator lint_off COMBDLY */
always @(X)
always @(X)
        xi <= X;
        xi <= X;
 
 
//
//
// Conversion unsigned to signed
// Conversion unsigned to signed
//
//
always @(Y)
always @(Y)
        yi <= Y;
        yi <= Y;
 
 /* verilator lint_on COMBDLY */
//
//
// First multiply stage
// First multiply stage
//
//
always @(posedge CLK or posedge RST)
always @(posedge CLK or posedge RST)
        if (RST)
        if (RST)

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