| Line 203... |
Line 203... |
reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
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reg sr_reg_bit_eph; // SR_EPH bit
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reg sr_reg_bit_eph; // SR_EPH bit
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reg sr_reg_bit_eph_select; // SR_EPH select
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reg sr_reg_bit_eph_select; // SR_EPH select
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wire sr_reg_bit_eph_muxed; // SR_EPH muxed bit
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wire sr_reg_bit_eph_muxed; // SR_EPH muxed bit
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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/* verilator lint_off UNOPTFLAT */
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reg write_spr; // Write SPR
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reg write_spr; // Write SPR
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reg read_spr; // Read SPR
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reg read_spr; // Read SPR
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/* verilator lint_on UNOPTFLAT */
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reg [width-1:0] to_wbmux; // For l.mfspr
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reg [width-1:0] to_wbmux; // For l.mfspr
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wire cfgr_sel; // Select for cfg regs
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wire cfgr_sel; // Select for cfg regs
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wire rf_sel; // Select for RF
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wire rf_sel; // Select for RF
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wire npc_sel; // Select for NPC
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wire npc_sel; // Select for NPC
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wire ppc_sel; // Select for PPC
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wire ppc_sel; // Select for PPC
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| Line 256... |
Line 258... |
assign spr_we = du_write | write_spr;
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assign spr_we = du_write | write_spr;
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//
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//
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// Qualify chip selects
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// Qualify chip selects
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//
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//
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/* verilator lint_off UNOPTFLAT */
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assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
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assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
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/* verilator lint_on UNOPTFLAT */
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//
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//
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// Decoding of groups
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// Decoding of groups
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//
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//
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always @(spr_addr)
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always @(spr_addr)
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case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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