URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [OR1K_startup.v] - Diff between revs 19 and 45

Rev 19	Rev 45
Line 50...	Line 50...
`always @ (posedge wb_clk or posedge wb_rst)`	`always @ (posedge wb_clk or posedge wb_rst)`
`if (wb_rst)`	`if (wb_rst)`
`wb_dat_o <= 32'h15000000;`	`wb_dat_o <= 32'h15000000;`
`else`	`else`
`case (wb_adr_i)`	`case (wb_adr_i)`
	`ifdef USE_SDRAM
`0 : wb_dat_o <= 32'h18000000;`	`0 : wb_dat_o <= 32'h18000000;`
`1 : wb_dat_o <= 32'hA8200000;`	`1 : wb_dat_o <= 32'hA8200000;`
`2 : wb_dat_o <= 32'h1880B000;`	`2 : wb_dat_o <= 32'h1880B000;`
`3 : wb_dat_o <= 32'hA8A00520;`	`3 : wb_dat_o <= 32'hA8A00520;`
`4 : wb_dat_o <= 32'hA8600001;`	`4 : wb_dat_o <= 32'hA8600001;`
Line 82...	Line 83...
`27 : wb_dat_o <= 32'hBC030520;`	`27 : wb_dat_o <= 32'hBC030520;`
`28 : wb_dat_o <= 32'h13FFFFFE;`	`28 : wb_dat_o <= 32'h13FFFFFE;`
`29 : wb_dat_o <= 32'h15000000;`	`29 : wb_dat_o <= 32'h15000000;`
`30 : wb_dat_o <= 32'h44004800;`	`30 : wb_dat_o <= 32'h44004800;`
`31 : wb_dat_o <= 32'h84640000;`	`31 : wb_dat_o <= 32'h84640000;`
	`else // !`ifdef USE_SDRAM
	`// Zero r0 and jump to 0x00000100`
	`0 : wb_dat_o <= 32'h18000000;`
	`1 : wb_dat_o <= 32'hA8200000;`
	`2 : wb_dat_o <= 32'hA8C00100;`
	`3 : wb_dat_o <= 32'h44003000;`
	`4 : wb_dat_o <= 32'h15000000;`
	`endif // !`ifdef USE_SDRAM
`endcase`	`endcase`
`always @ (posedge wb_clk or posedge wb_rst)`	`always @ (posedge wb_clk or posedge wb_rst)`
`if (wb_rst)`	`if (wb_rst)`
`wb_ack_o <= 1'b0;`	`wb_ack_o <= 1'b0;`
`else`	`else`