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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [OR1K_startup_generic.v] - Diff between revs 19 and 34

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Rev 19 Rev 34
Line 17... Line 17... 
       wb_dat_o <= 32'h15000000;
 
       wb_dat_o <= 32'h15000000;
 
     else
 
     else
 
       case (wb_adr_i)
 
       case (wb_adr_i)
 
          0 : wb_dat_o <= 32'h18000000;
 
          0 : wb_dat_o <= 32'h18000000;
 
          1 : wb_dat_o <= 32'hA8200000;
 
          1 : wb_dat_o <= 32'hA8200000;
 
          2 : wb_dat_o <= 32'h1880`SPI_BASE_MSB;
 
          2 : wb_dat_o <= { 16'h1880, 16'h`SPI_BASE_MSB } ;
 
          3 : wb_dat_o <= 32'hA8A00520;
 
          3 : wb_dat_o <= 32'hA8A00520;
 
          4 : wb_dat_o <= 32'hA8600001;
 
          4 : wb_dat_o <= 32'hA8600001;
 
          5 : wb_dat_o <= 32'h04000014;
 
          5 : wb_dat_o <= 32'h04000014;
 
          6 : wb_dat_o <= 32'hD4041818;
 
          6 : wb_dat_o <= 32'hD4041818;
 
          7 : wb_dat_o <= 32'h04000012;
 
          7 : wb_dat_o <= 32'h04000012;

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