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//////////////////////////////////////////////////////////////////////
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//// ////
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//// spi_top.v ////
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//// ////
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//// This file is part of the SPI IP core project ////
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//// http://www.opencores.org/projects/spi/ ////
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//// ////
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//// Author(s): ////
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//// - Simon Srot (simons@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "spi_defines.v"
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`include "timescale.v"
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module spi_flash_top
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(
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// Wishbone signals
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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// SPI signals
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ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
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);
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parameter divider_len = 2;
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parameter divider = 0;
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parameter Tp = 1;
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// Wishbone signals
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input wb_clk_i; // master clock input
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input wb_rst_i; // synchronous active high reset
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input [4:2] wb_adr_i; // lower address bits
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input [31:0] wb_dat_i; // databus input
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output [31:0] wb_dat_o; // databus output
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input [3:0] wb_sel_i; // byte select inputs
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input wb_we_i; // write enable input
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input wb_stb_i; // stobe/core select signal
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input wb_cyc_i; // valid bus cycle input
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output wb_ack_o; // bus cycle acknowledge output
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// SPI signals
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output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
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output sclk_pad_o; // serial clock
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output mosi_pad_o; // master out slave in
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input miso_pad_i; // master in slave out
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reg [31:0] wb_dat_o;
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reg wb_ack_o;
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// Internal signals
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// reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register
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wire [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
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reg [`SPI_SS_NB-1:0] ss; // Slave select register
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wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
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wire [5:0] char_len;
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reg char_len_ctrl; // char len
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reg go; // go
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wire spi_ctrl_sel; // ctrl register select
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wire spi_tx_sel; // tx_l register select
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wire spi_ss_sel; // ss register select
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wire tip; // transfer in progress
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wire pos_edge; // recognize posedge of sclk
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wire neg_edge; // recognize negedge of sclk
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wire last_bit; // marks last character bit
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wire rx_negedge; // miso is sampled on negative edge
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wire tx_negedge; // mosi is driven on negative edge
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wire lsb; // lsb first on line
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wire ass; // automatic slave select
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// Address decoder
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assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
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assign spi_tx_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
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assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
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// Read from registers
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// Wb data out
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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wb_dat_o <= #Tp 32'b0;
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else
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case (wb_adr_i[`SPI_OFS_BITS])
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`SPI_RX_0: wb_dat_o <= rx;
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`SPI_CTRL: wb_dat_o <= {18'd0, ctrl};
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`SPI_DEVIDE: wb_dat_o <= divider;//{{32-divider_len{1'b0}}, divider}; -- icarus couldn't compile original -- jb
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`SPI_SS: wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss};
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default: wb_dat_o <= rx;
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endcase
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end
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// Wb acknowledge
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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wb_ack_o <= #Tp 1'b0;
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else
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wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
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end
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// Ctrl register
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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{go,char_len_ctrl} <= #Tp 2'b01;
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else if(spi_ctrl_sel && wb_we_i && !tip)
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begin
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if (wb_sel_i[0])
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char_len_ctrl <= #Tp wb_dat_i[5];
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if (wb_sel_i[1])
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go <= #Tp wb_dat_i[8];
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end
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else if(tip && last_bit && pos_edge)
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go <= #Tp 1'b0;
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end
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assign char_len = char_len_ctrl ? 6'd32 : 6'd8;
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`ifdef SPI_CTRL_ASS
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assign ass = 1'b1;
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`else
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assign ass = 1'b0;
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`endif
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`ifdef SPI_CTRL_LSB
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assign lsb = 1'b1;
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`else
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assign lsb = 1'b0;
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`endif
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`ifdef SPI_CTRL_RX_NEGEDGE
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assign rx_negedge = 1'b1;
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`else
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assign rx_negedge = 1'b0;
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`endif
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`ifdef SPI_CTRL_TX_NEGEDGE
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assign tx_negedge = 1'b1;
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`else
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assign tx_negedge = 1'b1;
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`endif
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assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
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// Slave select register
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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ss <= #Tp {`SPI_SS_NB{1'b0}};
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else if(spi_ss_sel && wb_we_i && !tip)
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if (wb_sel_i[0])
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ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
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assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
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spi_flash_clgen
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#
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(
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.divider_len(divider_len),
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.divider(divider)
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)
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clgen
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(
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.clk_in(wb_clk_i),
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.rst(wb_rst_i),
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.go(go),
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.enable(tip),
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.last_clk(last_bit),
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.clk_out(sclk_pad_o),
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.pos_edge(pos_edge),
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.neg_edge(neg_edge)
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);
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spi_flash_shift shift
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(
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
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.latch(spi_tx_sel & wb_we_i),
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.byte_sel(wb_sel_i),
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.go(go),
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.pos_edge(pos_edge),
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.neg_edge(neg_edge),
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.lsb(lsb),
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.rx_negedge(rx_negedge),
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.tx_negedge(tx_negedge),
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.tip(tip),
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.last(last_bit),
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.p_in(wb_dat_i),
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.p_out(rx),
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.s_clk(sclk_pad_o),
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.s_in(miso_pad_i),
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.s_out(mosi_pad_o)
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);
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endmodule
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