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Rev 42 |
| Line 41... |
Line 41... |
module smii_sync
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module smii_sync
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(
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(
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// SMII sync
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// SMII sync
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output sync,
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output sync,
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// internal
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// internal
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output reg [1:10] state,
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output reg [10:1] state, // Changed for verilator -- jb
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// clock amd reset
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// clock amd reset
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input clk,
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input clk,
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input rst
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input rst
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);
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);
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// sync shall go high every 10:th cycle
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// sync shall go high every 10:th cycle
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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state <= 10'b0000000001;
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state <= 10'b1000000000;
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else
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else
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state <= {state[10],state[1:9]};
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state <= {state[9:1],state[10]};
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assign sync = state[1];
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assign sync = state[1];
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endmodule // smii_sync
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endmodule // smii_sync
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