| Line 64... |
Line 64... |
`endif
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`endif
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`ifdef SMII_LINK
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`ifdef SMII_LINK
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output reg link,
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output reg link,
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`endif
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`endif
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// internal
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// internal
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input [1:10] state,
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input [10:1] state, // Change bit size declaration order, was [1:10], not verilator compatible: %Error: Unsupported: MSB < LSB of bit range: 1<10
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// clock and reset
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// clock and reset
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input clk,
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input clk,
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input rst
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input rst
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);
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);
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|
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reg [0:7] tx_data_reg;
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reg [7:0] tx_data_reg;
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reg tx_data_reg_valid;
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reg tx_data_reg_valid;
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reg a0;
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reg a0;
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reg state_data;
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reg state_data;
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|
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reg [3:0] rx_tmp;
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reg [3:0] rx_tmp;
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| Line 150... |
Line 150... |
if (!mtxen & !a0)
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if (!mtxen & !a0)
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tx_data_reg_valid <= 1'b0;
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tx_data_reg_valid <= 1'b0;
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else if (a0)
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else if (a0)
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tx_data_reg_valid <= 1'b1;
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tx_data_reg_valid <= 1'b1;
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if (mtxen & !a0)
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if (mtxen & !a0)
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tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
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//tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
|
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tx_data_reg[3:0] <= {mtxd[3],mtxd[2],mtxd[1],mtxd[0]}; // Changed for verilator -- jb
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else if (mtxen & a0)
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else if (mtxen & a0)
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tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
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//tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
|
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tx_data_reg[7:4] <= {mtxd[3],mtxd[2],mtxd[1],mtxd[0]}; // Changed for verilator -- jb
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end // if ((state[4] | state[9]) & (tx_cnt == 4'd0))
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end // if ((state[4] | state[9]) & (tx_cnt == 4'd0))
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|
|
|
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// state flag
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// state flag
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 166... |
Line 168... |
if (state[1] & (tx_cnt == 4'd0))
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if (state[1] & (tx_cnt == 4'd0))
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state_data <= tx_data_reg_valid;
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state_data <= tx_data_reg_valid;
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|
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assign tx = state[1] ? mtxerr :
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assign tx = state[1] ? mtxerr :
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state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
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state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
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state_data ? |(state[2:10] & tx_data_reg) :
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state_data ? |(state[10:2] & tx_data_reg) : // changed bit select order to 10:2 -- jb
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|(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});
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|(state[10:2] & {mtxerr,speed,duplex,link,jabber,3'b111}); // changed bit select order to 10:2 -- jb
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|
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Receive
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// Receive
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|
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
|
