URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [uart16550/] [uart_top.v] - Diff between revs 18 and 33

Rev 18	Rev 33
Line 324...	Line 324...
`.rstate (rstate[3:0]));`	`.rstate (rstate[3:0]));`
`endif	`endif

`initial`	`initial`
`begin`	`begin`
	`ifdef UART16550_SIM_OUTPUT
`ifdef DATA_BUS_WIDTH_8	`ifdef DATA_BUS_WIDTH_8
`$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");`	`$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");`
`else	`else
`$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");`	`$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");`
`endif	`endif
`ifdef UART_HAS_BAUDRATE_OUTPUT	`ifdef UART_HAS_BAUDRATE_OUTPUT
`$display("(%m) UART INFO: Has baudrate output\n");`	`$display("(%m) UART INFO: Has baudrate output\n");`
`else	`else
`$display("(%m) UART INFO: Doesn't have baudrate output\n");`	`$display("(%m) UART INFO: Doesn't have baudrate output\n");`
`endif	`endif
	`endif
`end`	`end`

`endmodule`	`endmodule // uart_top`




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