URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [wb_sdram_ctrl/] [delay.v] - Diff between revs 18 and 22

Rev 18	Rev 22
Line 1...	Line 1...
`timescale 1ns/1ns	`timescale 1ns/1ns
`module #`	`module delay #`
`(`	`(`
`parameter depth = 3,`	`parameter depth = 3,`
`parameter width = 2`	`width = 2`
`)`	`)`
`delay`
`(`	`(`
`input [width-1:0] d,`	`input [width-1:0] d,`
`output [width-1:0] q,`	`output [width-1:0] q,`
`input clear,`	`input clear,`
`input clk,`	`input clk,`
Line 17...	Line 17...

`integer i;`	`integer i;`
`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`for ( i=1; i < depth+1; i= i + 1)`	`for ( i=1; i < depth+1; i= i + 1)`
`dffs[i] <= {depth{1'b0}};`	`dffs[i] <= 0; //{depth{1'b0}};`
`else`	`else`
`if (clear)`	`if (clear)`
`for ( i=1; i < depth+1; i= i + 1)`	`for ( i=1; i < depth+1; i= i + 1)`
`dffs[i] <= {depth{1'b0}};`	`dffs[i] <= 0; //{depth{1'b0}};`
`else`	`else`
`begin`	`begin`
`dffs[1] <= d;`	`dffs[1] <= d;`
`for ( i=2; i < depth+1; i= i + 1)`	`for ( i=2; i < depth+1; i= i + 1)`
`dffs[i] <= dffs[i-1];`	`dffs[i] <= dffs[i-1];`
Line 34...	Line 34...
`assign q = dffs[depth];`	`assign q = dffs[depth];`

`endmodule //`	`endmodule //`


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