URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [wb_sdram_ctrl/] [wb_sdram_ctrl.v] - Diff between revs 42 and 43

Rev 42	Rev 43
Line 27...	Line 27...
`input wb_rst`	`input wb_rst`
`);`	`);`

`reg ref_req;`	`reg ref_req;`
`wire ref_ack;`	`wire ref_ack;`
	`/* verilator lint_off UNOPTFLAT */`
`wire rd_ack, rd_ack_o, wr_ack, wr_ack_o, cmd_ack;`	`wire rd_ack, rd_ack_o, wr_ack, wr_ack_o, cmd_ack;`
	`/* verilator lint_on UNOPTFLAT */`
reg [`BA_SIZE-1:0] ba;	reg [`BA_SIZE-1:0] ba;
reg [`ROW_SIZE-1:0] row;	reg [`ROW_SIZE-1:0] row;

`// terminate current cycle if !stb&!cyc, empty fifo`	`// terminate current cycle if !stb&!cyc, empty fifo`
`// restart if adr_fail (non consecutive adr inc), empty fifo`	`// restart if adr_fail (non consecutive adr inc), empty fifo`
Line 209...	Line 209...


`assign terminate = ~wb_cyc_i & ~wb_stb_i;`	`assign terminate = ~wb_cyc_i & ~wb_stb_i;`
assign adr_fail = ~(wb_adr_i[`WB_ADR_HI:4]=={ba,row,burst_counter[`COL_SIZE-1:3]});	assign adr_fail = ~(wb_adr_i[`WB_ADR_HI:4]=={ba,row,burst_counter[`COL_SIZE-1:3]});
`assign clear = adr_fail & rd_ack_o;`	`assign clear = adr_fail & rd_ack_o;`
	`/* verilator lint_off UNOPTFLAT */`
`assign wb_ack_o = (rd_ack_o & !adr_fail) \| wr_ack_o;`	`assign wb_ack_o = (rd_ack_o & !adr_fail) \| wr_ack_o;`
	`/* verilator lint_on UNOPTFLAT */`
`endmodule // wb_sdram_ctrl`	`endmodule // wb_sdram_ctrl`

`No newline at end of file`	`No newline at end of file`