URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [orpsoc_top.v] - Diff between revs 40 and 42

Rev 40	Rev 42
Line 342...	Line 342...
`assign pic_ints[4] = 1'b0;`	`assign pic_ints[4] = 1'b0;`
`assign pic_ints[3] = 1'b0;`	`assign pic_ints[3] = 1'b0;`
`assign pic_ints[2] = uart0_irq;`	`assign pic_ints[2] = uart0_irq;`
`assign pic_ints[1] = 1'b0;`	`assign pic_ints[1] = 1'b0;`
`assign pic_ints[0] = 1'b0;`	`assign pic_ints[0] = 1'b0;`
`or1k i_or1k`	`or1k_top i_or1k`
`(`	`(`
`.clk_i (wb_clk),`	`.clk_i (wb_clk),`
`.rst_i (wb_rst),`	`.rst_i (wb_rst),`
`.pic_ints_i (pic_ints[19:0]),`	`.pic_ints_i (pic_ints[19:0]),`
`.iwb_clk_i (wb_clk),`	`.iwb_clk_i (wb_clk),`
Line 498...	Line 498...
`wire [3:0] m1rxd;`	`wire [3:0] m1rxd;`
`wire m1rxdv;`	`wire m1rxdv;`
`wire m1rxerr;`	`wire m1rxerr;`
`wire m1coll;`	`wire m1coll;`
`wire m1crs;`	`wire m1crs;`
`wire [1:10] state;`	`//wire [1:10] state;`
	`wire [10:1] state; // Changed for verilator -- jb`
`wire sync;`	`wire sync;`
`wire [1:1] rx, tx;`	`wire [1:1] rx, tx;`
`wire [1:1] mdc_o, md_i, md_o, md_oe;`	`wire [1:1] mdc_o, md_i, md_o, md_oe;`
`smii_sync smii_sync1`	`smii_sync smii_sync1`
`(`	`(`