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[/] [test_project/] [trunk/] [rtl/] [verilog/] [orpsoc_top.v] - Diff between revs 42 and 45

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Rev 42 Rev 45
Line 438... Line 438...
assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1;
assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1;
assign spi_sd_ss_pad_o   =  spi_flash_ss[1];
assign spi_sd_ss_pad_o   =  spi_flash_ss[1];
assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i :
assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i :
                        !spi_flash_ss[1] ? spi_sd_miso_pad_i :
                        !spi_flash_ss[1] ? spi_sd_miso_pad_i :
                        1'b0;
                        1'b0;
 
`ifdef USE_SDRAM
  wb_sdram_ctrl wb_sdram_ctrl0
  wb_sdram_ctrl wb_sdram_ctrl0
  (
  (
    .wb_dat_i(wbs_mc_m_dat_i),
    .wb_dat_i(wbs_mc_m_dat_i),
    .wb_dat_o(wbs_mc_m_dat_o),
    .wb_dat_o(wbs_mc_m_dat_o),
    .wb_sel_i(wbs_mc_m_sel_i),
    .wb_sel_i(wbs_mc_m_sel_i),
Line 462... Line 463...
    .sdr_dqm_o(mem_dqm_pad_o),
    .sdr_dqm_o(mem_dqm_pad_o),
    .sdram_clk(wb_clk),
    .sdram_clk(wb_clk),
    .wb_clk(wb_clk),
    .wb_clk(wb_clk),
    .wb_rst(wb_rst)
    .wb_rst(wb_rst)
   );
   );
 
`else // !`ifdef USE_SDRAM
 
 
 
   parameter ram_wb_dat_width = 32;
 
   parameter ram_wb_adr_width = 24;
 
   parameter ram_wb_mem_size  = 2097152; // 8MB
 
 
 
  ram_wb
 
    #
 
    (
 
     .dat_width(ram_wb_dat_width),
 
     .adr_width(ram_wb_adr_width),
 
     .mem_size(ram_wb_mem_size)
 
     )
 
   ram_wb0
 
   (
 
    .dat_i(wbs_mc_m_dat_i),
 
    .dat_o(wbs_mc_m_dat_o),
 
    .sel_i(wbs_mc_m_sel_i),
 
    .adr_i(wbs_mc_m_adr_i[ram_wb_adr_width-1:2]),
 
    .we_i (wbs_mc_m_we_i),
 
    .cti_i(wbs_mc_m_cti_i),
 
    .stb_i(wbs_mc_m_stb_i),
 
    .cyc_i(wbs_mc_m_cyc_i),
 
    .ack_o(wbs_mc_m_ack_o),
 
    .clk_i(wb_clk),
 
    .rst_i(wb_rst)
 
   );
 
 
 
   assign mem_cke_pad_o = 1;
 
   assign mem_cs_pad_o = 1;
 
   assign mem_ras_pad_o = 1;
 
   assign mem_cas_pad_o = 1;
 
   assign mem_we_pad_o = 1;
 
   assign mem_adr_pad_o = 0;
 
   assign mem_ba_pad_o = 0;
 
   assign mem_dat_pad_io = 32'hzzzzzzzz;
 
   assign mem_dqm_pad_o = 0;
 
 
 
`endif // !`ifdef USE_SDRAM
 
 
assign wbs_mc_m_err_o = 1'b0;
assign wbs_mc_m_err_o = 1'b0;
 
 
     uart_top
     uart_top
     #( 32, 5)
     #( 32, 5)
   i_uart_0_top
   i_uart_0_top
     (
     (
      .wb_dat_o   (wbs_uart0_dat_o),
      .wb_dat_o   (wbs_uart0_dat_o),

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