| Line 1... |
Line 1... |
//module ref_design_top
|
//module ref_design_top
|
module orpsoc_top
|
module orpsoc_top
|
(
|
(
|
output spi_flash_sclk_pad_o ,
|
|
output spi_flash_ss_pad_o ,
|
|
input spi_flash_miso_pad_i ,
|
|
output spi_flash_mosi_pad_o ,
|
|
output spi_flash_w_n_pad_o ,
|
|
output spi_flash_hold_n_pad_o,
|
|
output spi_sd_sclk_pad_o ,
|
output spi_sd_sclk_pad_o ,
|
output spi_sd_ss_pad_o ,
|
output spi_sd_ss_pad_o ,
|
input spi_sd_miso_pad_i ,
|
input spi_sd_miso_pad_i ,
|
output spi_sd_mosi_pad_o ,
|
output spi_sd_mosi_pad_o ,
|
|
`ifdef USE_SDRAM
|
|
// SDRAM bus signals
|
inout [15:0] mem_dat_pad_io,
|
inout [15:0] mem_dat_pad_io,
|
output [12:0] mem_adr_pad_o ,
|
output [12:0] mem_adr_pad_o ,
|
output [1:0] mem_dqm_pad_o ,
|
output [1:0] mem_dqm_pad_o ,
|
output [1:0] mem_ba_pad_o ,
|
output [1:0] mem_ba_pad_o ,
|
output mem_cs_pad_o ,
|
output mem_cs_pad_o ,
|
output mem_ras_pad_o ,
|
output mem_ras_pad_o ,
|
output mem_cas_pad_o ,
|
output mem_cas_pad_o ,
|
output mem_we_pad_o ,
|
output mem_we_pad_o ,
|
output mem_cke_pad_o ,
|
output mem_cke_pad_o ,
|
|
// SPI bus signals for flash memory
|
|
output spi_flash_sclk_pad_o ,
|
|
output spi_flash_ss_pad_o ,
|
|
input spi_flash_miso_pad_i ,
|
|
output spi_flash_mosi_pad_o ,
|
|
output spi_flash_w_n_pad_o ,
|
|
output spi_flash_hold_n_pad_o,
|
|
`endif // `ifdef USE_SDRAM
|
|
`ifdef USE_ETHERNET
|
output [1:1] eth_sync_pad_o,
|
output [1:1] eth_sync_pad_o,
|
output [1:1] eth_tx_pad_o,
|
output [1:1] eth_tx_pad_o,
|
input [1:1] eth_rx_pad_i,
|
input [1:1] eth_rx_pad_i,
|
input eth_clk_pad_i,
|
input eth_clk_pad_i,
|
inout [1:1] eth_md_pad_io,
|
inout [1:1] eth_md_pad_io,
|
output [1:1] eth_mdc_pad_o,
|
output [1:1] eth_mdc_pad_o,
|
|
`endif // `ifdef USE_ETHERNET
|
output spi1_mosi_pad_o,
|
output spi1_mosi_pad_o,
|
input spi1_miso_pad_i,
|
input spi1_miso_pad_i,
|
output spi1_ss_pad_o ,
|
output spi1_ss_pad_o ,
|
output spi1_sclk_pad_o,
|
output spi1_sclk_pad_o,
|
|
`ifdef DISABLE_IOS_FOR_VERILATOR
|
|
output [8-1:0] gpio_a_pad_io,
|
|
`else
|
inout [8-1:0] gpio_a_pad_io,
|
inout [8-1:0] gpio_a_pad_io,
|
|
`endif
|
input uart0_srx_pad_i ,
|
input uart0_srx_pad_i ,
|
output uart0_stx_pad_o ,
|
output uart0_stx_pad_o ,
|
input dbg_tdi_pad_i,
|
input dbg_tdi_pad_i,
|
input dbg_tck_pad_i,
|
input dbg_tck_pad_i,
|
input dbg_tms_pad_i,
|
input dbg_tms_pad_i,
|
| Line 427... |
Line 437... |
.mosi_pad_o(spi_flash_mosi),
|
.mosi_pad_o(spi_flash_mosi),
|
.miso_pad_i(spi_flash_miso),
|
.miso_pad_i(spi_flash_miso),
|
.sclk_pad_o(spi_flash_sclk),
|
.sclk_pad_o(spi_flash_sclk),
|
.ss_pad_o(spi_flash_ss)
|
.ss_pad_o(spi_flash_ss)
|
);
|
);
|
assign spi_flash_mosi_pad_o = !spi_flash_ss[0] ? spi_flash_mosi : 1'b1;
|
|
assign spi_flash_sclk_pad_o = !spi_flash_ss[0] ? spi_flash_sclk : 1'b1;
|
|
assign spi_flash_ss_pad_o = spi_flash_ss[0];
|
|
assign spi_flash_w_n_pad_o = 1'b1;
|
|
assign spi_flash_hold_n_pad_o = 1'b1;
|
|
assign spi_sd_mosi_pad_o = !spi_flash_ss[1] ? spi_flash_mosi : 1'b1;
|
|
assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1;
|
|
assign spi_sd_ss_pad_o = spi_flash_ss[1];
|
|
assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i :
|
|
!spi_flash_ss[1] ? spi_sd_miso_pad_i :
|
|
1'b0;
|
|
`ifdef USE_SDRAM
|
`ifdef USE_SDRAM
|
wb_sdram_ctrl wb_sdram_ctrl0
|
wb_sdram_ctrl wb_sdram_ctrl0
|
(
|
(
|
.wb_dat_i(wbs_mc_m_dat_i),
|
.wb_dat_i(wbs_mc_m_dat_i),
|
.wb_dat_o(wbs_mc_m_dat_o),
|
.wb_dat_o(wbs_mc_m_dat_o),
|
| Line 463... |
Line 464... |
.sdr_dqm_o(mem_dqm_pad_o),
|
.sdr_dqm_o(mem_dqm_pad_o),
|
.sdram_clk(wb_clk),
|
.sdram_clk(wb_clk),
|
.wb_clk(wb_clk),
|
.wb_clk(wb_clk),
|
.wb_rst(wb_rst)
|
.wb_rst(wb_rst)
|
);
|
);
|
|
|
|
// SPI flash memory signals
|
|
assign spi_flash_mosi_pad_o = !spi_flash_ss[0] ? spi_flash_mosi : 1'b1;
|
|
assign spi_flash_sclk_pad_o = !spi_flash_ss[0] ? spi_flash_sclk : 1'b1;
|
|
assign spi_flash_ss_pad_o = spi_flash_ss[0];
|
|
assign spi_flash_w_n_pad_o = 1'b1;
|
|
assign spi_flash_hold_n_pad_o = 1'b1;
|
|
assign spi_sd_mosi_pad_o = !spi_flash_ss[1] ? spi_flash_mosi : 1'b1;
|
|
assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1;
|
|
assign spi_sd_ss_pad_o = spi_flash_ss[1];
|
|
assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i :
|
|
!spi_flash_ss[1] ? spi_sd_miso_pad_i :
|
|
1'b0;
|
|
|
`else // !`ifdef USE_SDRAM
|
`else // !`ifdef USE_SDRAM
|
|
|
parameter ram_wb_dat_width = 32;
|
parameter ram_wb_dat_width = 32;
|
parameter ram_wb_adr_width = 24;
|
parameter ram_wb_adr_width = 24;
|
parameter ram_wb_mem_size = 2097152; // 8MB
|
parameter ram_wb_mem_size = 2097152; // 8MB
|
| Line 491... |
Line 506... |
.ack_o(wbs_mc_m_ack_o),
|
.ack_o(wbs_mc_m_ack_o),
|
.clk_i(wb_clk),
|
.clk_i(wb_clk),
|
.rst_i(wb_rst)
|
.rst_i(wb_rst)
|
);
|
);
|
|
|
assign mem_cke_pad_o = 1;
|
|
assign mem_cs_pad_o = 1;
|
|
assign mem_ras_pad_o = 1;
|
|
assign mem_cas_pad_o = 1;
|
|
assign mem_we_pad_o = 1;
|
|
assign mem_adr_pad_o = 0;
|
|
assign mem_ba_pad_o = 0;
|
|
assign mem_dat_pad_io = 32'hzzzzzzzz;
|
|
assign mem_dqm_pad_o = 0;
|
|
|
|
`endif // !`ifdef USE_SDRAM
|
`endif // !`ifdef USE_SDRAM
|
|
|
assign wbs_mc_m_err_o = 1'b0;
|
assign wbs_mc_m_err_o = 1'b0;
|
|
|
uart_top
|
uart_top
|
| Line 530... |
Line 535... |
.dcd_pad_i (1'b0),
|
.dcd_pad_i (1'b0),
|
.dsr_pad_i (1'b0),
|
.dsr_pad_i (1'b0),
|
.ri_pad_i (1'b0)
|
.ri_pad_i (1'b0)
|
);
|
);
|
assign gpio_a_pad_io[7:0] = 8'hfe;
|
assign gpio_a_pad_io[7:0] = 8'hfe;
|
|
|
|
`ifdef USE_ETHERNET
|
wire m1tx_clk;
|
wire m1tx_clk;
|
wire [3:0] m1txd;
|
wire [3:0] m1txd;
|
wire m1txen;
|
wire m1txen;
|
wire m1txerr;
|
wire m1txerr;
|
wire m1rx_clk;
|
wire m1rx_clk;
|
| Line 643... |
Line 650... |
.pad(eth_rx_pad_i[1]),
|
.pad(eth_rx_pad_i[1]),
|
.q(rx[1]),
|
.q(rx[1]),
|
.clk(eth_clk),
|
.clk(eth_clk),
|
.rst(wb_rst)
|
.rst(wb_rst)
|
);
|
);
|
|
`else // !`ifdef USE_ETHERNET
|
|
// Tie off WB arbitor inputs
|
|
assign wbs_eth1_cfg_dat_o = 0;
|
|
assign wbs_eth1_cfg_ack_o = 0;
|
|
assign wbs_eth1_cfg_err_o = 0;
|
|
assign wbm_eth1_adr_o = 0;
|
|
assign wbm_eth1_sel_o = 0;
|
|
assign wbm_eth1_we_o = 0;
|
|
assign wbm_eth1_dat_o = 0;
|
|
assign wbm_eth1_cyc_o = 0;
|
|
assign wbm_eth1_stb_o = 0;
|
|
assign wbm_eth1_cti_o = 0;
|
|
assign wbm_eth1_bte_o = 0;
|
|
`endif // `ifdef USE_ETHERNET
|
|
|
dummy_slave
|
dummy_slave
|
# ( .value(32'hc0000000))
|
# ( .value(32'hc0000000))
|
ds1
|
ds1
|
(
|
(
|
.dat_o(wbs_ds1_dat_o),
|
.dat_o(wbs_ds1_dat_o),
|
| Line 674... |
Line 696... |
.LOCK (pll_lock),
|
.LOCK (pll_lock),
|
.GLA(wb_clk),
|
.GLA(wb_clk),
|
.GLB(usbClk_pll),
|
.GLB(usbClk_pll),
|
.GLC()
|
.GLC()
|
);
|
);
|
|
|
assign rst_pad_o = pll_lock;
|
assign rst_pad_o = pll_lock;
|
|
|
gbuf gbufi1
|
gbuf gbufi1
|
(
|
(
|
.CLK(~(pll_lock & rst_pad_i)),
|
.CLK(~(pll_lock & rst_pad_i)),
|
.GL(wb_rst));
|
.GL(wb_rst));
|
gbuf gbufi2
|
gbuf gbufi2
|
| Line 691... |
Line 715... |
.GL(usbClk));
|
.GL(usbClk));
|
gbuf gbufi4
|
gbuf gbufi4
|
(
|
(
|
.CLK(eth_clk_pad_i),
|
.CLK(eth_clk_pad_i),
|
.GL(eth_clk));
|
.GL(eth_clk));
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
