| Line 95... |
Line 95... |
SIM_SUCCESS_MESSAGE=deaddead
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SIM_SUCCESS_MESSAGE=deaddead
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|
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.PHONY: prepare_rtl
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.PHONY: prepare_rtl
|
prepare_rtl:
|
prepare_rtl:
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
|
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
|
|
|
.PHONY: prepare_sw
|
.PHONY: prepare_sw
|
prepare_sw:
|
prepare_sw:
|
@$(MAKE) -C $(SW_DIR)/support
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@$(MAKE) -C $(SW_DIR)/support
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@$(MAKE) -C $(SW_DIR)/utils
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@$(MAKE) -C $(SW_DIR)/utils
|
| Line 171... |
Line 172... |
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
fi; \
|
fi; \
|
echo ; \
|
echo ; \
|
echo "\t#### Compiling RTL ####"; \
|
echo "\t#### Compiling RTL ####"; \
|
rm -f $(SIM_RUN_DIR)/a.out; \
|
rm -f $(SIM_RUN_DIR)/a.out; \
|
$(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
|
$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
|
echo; \
|
echo; \
|
echo "\t#### Beginning simulation ####"; \
|
echo "\t#### Beginning simulation ####"; \
|
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
|
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
| Line 264... |
Line 265... |
else echo "\t#### Test $$TEST FAILED ####";\
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else echo "\t#### Test $$TEST FAILED ####";\
|
fi; \
|
fi; \
|
echo "\t####"; echo; \
|
echo "\t####"; echo; \
|
done
|
done
|
|
|
prepare_vlt:
|
prepare_vlt: prepare_rtl
|
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_RUN_DIR)/$(VLT_COMMAND_FILE).generated \
|
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_RUN_DIR)/$(VLT_COMMAND_FILE).generated \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
