| Line 91... |
Line 91... |
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ICARUS=iverilog
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ICARUS=iverilog
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ICARUS_VVP=vvp
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ICARUS_VVP=vvp
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ICARUS_COMMAND_FILE=icarus.scr
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ICARUS_COMMAND_FILE=icarus.scr
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VLT_COMMAND_FILE=verilator.scr
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VLT_COMMAND_FILE=verilator.scr
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SIM_MEM_FILE="flash.in"
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SIM_SUCCESS_MESSAGE=deaddead
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SIM_SUCCESS_MESSAGE=deaddead
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# If USE_SDRAM is defined we'll add it to the simulator's defines on the
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# command line becuase it's used by many different modules and it's easier
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# to do it this way than make them all include a file.
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ifdef USE_SDRAM
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RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
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endif
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SIM_FLASH_MEM_FILE="flash.in"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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SIM_SRAM_MEM_FILE="sram.vmem"
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.PHONY: prepare_rtl
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.PHONY: prepare_rtl
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prepare_rtl:
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prepare_rtl:
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@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
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@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
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| Line 111... |
Line 120... |
# compiled, and then the software library files.
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# compiled, and then the software library files.
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# Next the few verilog files that need preperation are taken care of.
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# Next the few verilog files that need preperation are taken care of.
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# The test begins by starting a loop in bash using on the strings defined in
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# The test begins by starting a loop in bash using on the strings defined in
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# TESTS. Each one corresponds to a certain module of software for the OpenRISC
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# TESTS. Each one corresponds to a certain module of software for the OpenRISC
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# that is included in this test suite. Under the sw/ path is a set of paths,
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# that is included in this test suite. Under the sw/ path is a set of paths,
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# and all except the support/ and utils/ paths contain code which is run to test
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# and all except the support/ and utils/ paths contain code which is run to
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# the OR1k used in this test suite. For each of these software modules, it is
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# test the OR1k used in this test suite. For each of these software modules,
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# possible that different tests are done using the same module. These tests can
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# it is possible that different tests are done using the same module. These
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# vary by either using different levels of optimisation during compilation,
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# tests can vary by either using different levels of optimisation during
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# and/or by having the OR1k's caches enabled or disabled.
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# compilation, and/or by having the OR1k's caches enabled or disabled.
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# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
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# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
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# usually just ../results, log files, and optionally VCD files, are created for
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# usually just ../results, log files, and optionally VCD files, are created for
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# inspection later and are named according to the test. Inspect the file
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# inspection later and are named according to the test. Inspect the file
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# bench/verilog/or1200_monitor.v to find out in detail what each log consists of.
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# bench/verilog/or1200_monitor.v to find out in detail what each log consists
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# of.
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# For each test, a few things occur. First the software that will run inside
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# For each test, a few things occur. First the software that will run inside
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# the simulated OR1k system is compiled, converted to a format which can be read
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# the simulated OR1k system is compiled, converted to a format which can be
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# read
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# into the flash memory model via $readmemh() and linked to the sim/run
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# into the flash memory model via $readmemh() and linked to the sim/run
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# directory as $(SIM_MEM_FILE), which currently is flash.in. Next a compilation
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# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
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# script for icarus is generated, containing a list of all the RTL files and
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# compilation script for icarus is generated, containing a list of all the
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# include directories. Next, an include file for the verilog testbench is
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# RTL files and include directories. Next, an include file for the verilog
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# generated, containing a string of the name of the current test, path to the
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# testbench is generated, containing a string of the name of the current
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# results directory (for VCD generation) and any other things which might vary
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# test, path to the results directory (for VCD generation) and any other
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# from test to test. This is not done by +define lines in the icarus script
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# things which might vary from test to test. This is not done by +define
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# because of string handling incosistencies between different simulators and
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# lines in the icarus script because of string handling incosistencies
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# shells.
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# between different simulators and shells.
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# Once all the files are generated, icarus is called to compile the rtl design,
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# Once all the files are generated, icarus is called to compile the rtl
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# and then run it.
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# design, and then run it. Each of the tested software modules have code which
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# Each of the tested software modules have code which will trigger the
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# will trigger the simulation to be stopped by use of the l.nop instruction
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# simulation to be stopped by use of the l.nop instruction with an immediate
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# with an immediate value of 1. When the simulation finishes, the simulation
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# value of 1. When the simulation finishes, the simulation executable exits and
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# executable exits and the log of the simulation is inspected for the expected
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# the log of the simulation is inspected for the expected output. Currently, the
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# output. Currently, the string "deaddead" indicates that the software
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# string "deaddead" indicates that the software completed successfully. This is
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# completed successfully. This is counted as the ORPSoC "passing" the test. In
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# counted as the ORPSoC "passing" the test. In fact, whether the system did the
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# fact, whether the system did the right thing or not requires more
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# right thing or not requires more inspection, but roughly this is a good
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# inspection, but roughly this is a good indicator that nothing major went
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# indicator that nothing major went wrong.
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# wrong.
|
# Once the current test is finished, the next begins with the compilation of its
|
# Once the current test is finished, the next begins with the compilation of its
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# software and linking of the resulting hex file to the run path, etc.
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# software and linking of the resulting hex file to the run path, etc.
|
|
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
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|
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
|
|
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
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# Verilator defaults to internal memories
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rtl-tests: prepare_sw prepare_rtl
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rtl-tests: prepare_sw prepare_rtl
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@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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@echo
|
@echo
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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@echo
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| Line 155... |
Line 170... |
echo; \
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echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Compiling software ####"; echo; \
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echo "\t#### Compiling software ####"; echo; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
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rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
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| Line 202... |
Line 219... |
echo; \
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echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Compiling software ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
|
rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
if [ ! -z $$VCD ]; \
|
if [ ! -z $$VCD ]; \
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
fi; \
|
fi; \
|
|
if [ ! -z $$USE_SDRAM ]; then \
|
|
echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
|
|
fi; \
|
echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
if [ -z $$NO_SIM_LOGGING ]; then \
|
if [ -z $$NO_SIM_LOGGING ]; then \
|
