| Line 84... |
Line 84... |
SIM_VLT_DIR=$(SIM_DIR)/vlt
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SIM_VLT_DIR=$(SIM_DIR)/vlt
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BENCH_DIR=$(PROJECT_ROOT)/bench
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BENCH_DIR=$(PROJECT_ROOT)/bench
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BACKEND_DIR=$(PROJECT_ROOT)/backend
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BACKEND_DIR=$(PROJECT_ROOT)/backend
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
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BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
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RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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SW_DIR=$(PROJECT_ROOT)/sw
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SW_DIR=$(PROJECT_ROOT)/sw
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ICARUS=iverilog
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ICARUS=iverilog
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ICARUS_VVP=vvp
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ICARUS_VVP=vvp
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| Line 288... |
Line 290... |
echo "\t#### Test $$TEST PASSED ####";\
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echo "\t#### Test $$TEST PASSED ####";\
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else echo "\t#### Test $$TEST FAILED ####";\
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else echo "\t#### Test $$TEST FAILED ####";\
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fi; \
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fi; \
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echo "\t####"; echo; \
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echo "\t####"; echo; \
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done
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done
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SYSC_MODEL_FILES=$(BENCH_SYSC_SRC_DIR)/Or1200Monitor.cpp $(BENCH_SYSC_SRC_DIR)/ResetSC.cpp
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prepare_vlt: prepare_rtl
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prepare_vlt: $(SIM_VLT_DIR)/libmodules.a prepare_rtl
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if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
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if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
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# Generate the compile script to give Verilator
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cd $(SIM_VLT_DIR) && \
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cd $(SIM_VLT_DIR) && \
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sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(VLT_COMMAND_FILE).generated \
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sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(VLT_COMMAND_FILE).generated \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
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-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
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-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
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-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
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-e \\!^//.*\$$!d -e \\!^\$$!d;
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-e \\!^//.*\$$!d -e \\!^\$$!d;
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# Now call verilator to generate the .mk's
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cd $(SIM_VLT_DIR) && \
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cd $(SIM_VLT_DIR) && \
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verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc -f $(VLT_COMMAND_FILE).generated
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verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) $(SYSC_MODEL_FILES) -f $(VLT_COMMAND_FILE).generated
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# Now call the first makefile it generated
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cd $(SIM_VLT_DIR) && \
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cd $(SIM_VLT_DIR) && \
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$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
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$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
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# cd $(SIM_VLT_DIR) && \
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$(MAKE) -f Vorpsoc_top.mk sc_main.o
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cd $(SIM_VLT_DIR) && \
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cd $(SIM_VLT_DIR) && \
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$(MAKE) -f Vorpsoc_top.mk verilated.o
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$(MAKE) -f Vorpsoc_top.mk verilated.o
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cd $(SIM_VLT_DIR) && \
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cp Vorpsoc_top__ALL.a libVorpsoc_top.a
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# Now compile the top level systemC module
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# Now compile the top level systemC module
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cd $(SIM_VLD_DIR) && g++ -fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer -I$(BENCH_SYSC_DIR)/include -I$(SYSTEMC)/include -I$(VERILATOR_ROOT)/include -I$(SIM_VLT_DIR) -L$(SIM_VLT_DIR) -L$(SYSTEMC)/lib-linux64 $(BENCH_SYSC_DIR)/src/OrpsocMain.cpp
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cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
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# Order of libraries here is important
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cd $(SIM_VLT_DIR) && g++ -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
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# SystemC modules library
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$(SIM_VLT_DIR)/libmodules.a:
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$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
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|
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clean-sw:
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clean-sw:
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@for TEST in $(TESTS); do \
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@for TEST in $(TESTS); do \
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echo "Current test: $$TEST"; \
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echo "Current test: $$TEST"; \
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