| Line 291... |
Line 291... |
else echo "\t#### Test $$TEST FAILED ####";\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
fi; \
|
fi; \
|
echo "\t####"; echo; \
|
echo "\t####"; echo; \
|
done
|
done
|
|
|
|
# List of System C models - use this link to link the source into the Verilator
|
|
# build directory
|
SYSC_MODELS=OrpsocAccess TraceSC
|
SYSC_MODELS=OrpsocAccess TraceSC
|
|
|
|
# This is the list of extra models we'll issue make commands for
|
|
# Included is the SystemPerl trace model
|
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) SpTraceVcdC
|
|
|
prepare_vlt: $(SIM_VLT_DIR)/libmodules.a prepare_rtl
|
prepare_vlt: $(SIM_VLT_DIR)/libmodules.a prepare_rtl
|
if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
|
if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
|
# Generate the compile script to give Verilator
|
# Generate the compile script to give Verilator
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(VLT_COMMAND_FILE).generated \
|
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(VLT_COMMAND_FILE).generated \
|
| Line 312... |
Line 318... |
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
|
fi; \
|
fi; \
|
done
|
done
|
# Now call verilator to generate the .mk's
|
# Now call verilator to generate the .mk's
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
|
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
|
# Now call the first makefile it generated
|
# Now call the first makefile it generated
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
|
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
|
# Compile the module files
|
# Compile the module files
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
done
|
done
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
$(MAKE) -f Vorpsoc_top.mk verilated.o
|
$(MAKE) -f Vorpsoc_top.mk verilated.o
|
# cd $(SIM_VLT_DIR) && \
|
# cd $(SIM_VLT_DIR) && \
|
| Line 331... |
Line 337... |
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
|
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
|
ar rcs libVorpsoc_top.a verilated.o; \
|
ar rcs libVorpsoc_top.a verilated.o; \
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
|
ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
|
done
|
done
|
# Final linking of the simulation executable. Order of libraries here is important!
|
# Final linking of the simulation executable. Order of libraries here is important!
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
|
|
