| Line 105... |
Line 105... |
endif
|
endif
|
SIM_FLASH_MEM_FILE="flash.in"
|
SIM_FLASH_MEM_FILE="flash.in"
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
|
|
|
TESTS_PASSED=0
|
|
TESTS_PERFORMED=0;
|
|
|
|
################################################################################
|
|
# Event-driven simulator build rules (Icarus, NCSim)
|
|
################################################################################
|
|
|
.PHONY: prepare_rtl
|
.PHONY: prepare_rtl
|
prepare_rtl:
|
prepare_rtl:
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
|
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
|
|
|
|
|
|
ifdef UART_PRINTF
|
|
TEST_SW_MAKE_OPTS=UART_PRINTF=1
|
|
endif
|
|
|
.PHONY: prepare_sw
|
.PHONY: prepare_sw
|
prepare_sw:
|
prepare_sw:
|
@$(MAKE) -C $(SW_DIR)/support
|
@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
|
@$(MAKE) -C $(SW_DIR)/utils
|
@$(MAKE) -C $(SW_DIR)/utils all
|
|
|
|
|
# Rough guide to how these tests work:
|
# Rough guide to how these tests work:
|
# First, the couple of custom, required, software tools under sw/utils are
|
# First, the couple of custom, required, software tools under sw/utils are
|
# compiled, and then the software library files.
|
# compiled, and then the software library files.
|
# Next the few verilog files that need preperation are taken care of.
|
# Next the few verilog files that need preperation are taken care of.
|
| Line 171... |
Line 184... |
echo "################################################################################"; \
|
echo "################################################################################"; \
|
echo; \
|
echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
echo "\t#### Compiling software ####"; echo; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
|
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
|
| Line 201... |
Line 214... |
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
|
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
echo; echo "\t####"; \
|
echo; echo "\t####"; \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
echo "\t#### Test $$TEST PASSED ####";\
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
else echo "\t#### Test $$TEST FAILED ####";\
|
fi; \
|
fi; \
|
echo "\t####"; echo; \
|
echo "\t####"; echo; \
|
done
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
|
done; \
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
|
|
|
|
|
|
# Use NCSIM instead of icarus
|
# Use NCSIM instead of icarus
|
rtl-nc-tests: prepare_sw prepare_rtl
|
rtl-nc-tests: prepare_sw prepare_rtl
|
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
| Line 260... |
Line 276... |
echo "\t####"; echo; \
|
echo "\t####"; echo; \
|
done
|
done
|
|
|
|
|
|
|
vlt-tests: prepare_sw prepare_rtl prepare_vlt
|
################################################################################
|
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
# Verilator model build rules
|
@echo
|
################################################################################
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
|
@echo
|
|
@for TEST in $(TESTS); do \
|
|
echo "################################################################################"; \
|
|
echo; \
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
|
echo "\t#### Compiling software ####"; echo; \
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
|
|
echo ; \
|
|
echo "\t#### Compiling RTL ####"; \
|
|
rm -f $(SIM_RUN_DIR)/a.out; \
|
|
$(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
|
|
echo; \
|
|
echo "\t#### Beginning simulation ####"; \
|
|
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
|
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
|
echo; echo "\t####"; \
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
|
echo "\t#### Test $$TEST PASSED ####";\
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
|
fi; \
|
|
echo "\t####"; echo; \
|
|
done
|
|
|
|
# List of System C models - use this link to link the source into the Verilator
|
|
|
|
|
# List of System C models - use this list to link the sources into the Verilator
|
# build directory
|
# build directory
|
SYSC_MODELS=OrpsocAccess TraceSC
|
SYSC_MODELS=OrpsocAccess TraceSC
|
|
|
|
# Only need the trace target if we are tracing
|
|
ifneq (,$(findstring -trace, $(VLT_FLAGS)))
|
|
VLT_TRACEOBJ = SpTraceVcdC
|
|
endif
|
|
|
# This is the list of extra models we'll issue make commands for
|
# This is the list of extra models we'll issue make commands for
|
# Included is the SystemPerl trace model
|
# Included is the SystemPerl trace model
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) SpTraceVcdC
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
|
|
prepare_vlt: $(SIM_VLT_DIR)/libmodules.a prepare_rtl
|
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
|
if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
|
|
# Generate the compile script to give Verilator
|
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
|
|
# Final linking of the simulation executable. Order of libraries here is important!
|
|
@echo; echo "\tGenerating simulation executable"; echo
|
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
|
|
|
$(SIM_VLT_DIR)/OrpsocMain.o:
|
|
# Now compile the top level systemC "testbench" module
|
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
|
|
|
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
|
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
|
@echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
|
|
@cd $(SIM_VLT_DIR) && \
|
|
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
|
|
ar rcs libVorpsoc_top.a verilated.o; \
|
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
|
ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
|
|
done
|
|
|
|
$(SIM_VLT_DIR)/verilated.o:
|
|
@echo; echo "\tCompiling verilated.o"; echo
|
|
@cd $(SIM_VLT_DIR) && \
|
|
$(MAKE) -f Vorpsoc_top.mk verilated.o
|
|
|
|
.PHONY: vlt_modules_compile
|
|
vlt_modules_compile:
|
|
# Compile the module files
|
|
@echo; echo "\tCompiling SystemC models"
|
|
@cd $(SIM_VLT_DIR) && \
|
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
|
done
|
|
|
|
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
|
|
@echo; echo "\tCompiling main design"; echo
|
|
@cd $(SIM_VLT_DIR) && \
|
|
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
|
|
|
|
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
|
|
# Now call verilator to generate the .mk files
|
|
@echo; echo "\tCalling verilator"; echo
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(VLT_COMMAND_FILE).generated \
|
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
|
|
|
|
# SystemC modules library
|
|
$(SIM_VLT_DIR)/libmodules.a:
|
|
@echo; echo "\tCompiling SystemC modules"; echo
|
|
@$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
|
|
|
|
|
|
# Verilator command script
|
|
# Generate the compile script to give Verilator
|
|
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
|
|
@echo; echo "\tGenerating verilator compile script"; echo
|
|
@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
|
|
|
.PHONY: vlt_model_links
|
|
vlt_model_links:
|
# Link all the required system C model files into the verilator work dir
|
# Link all the required system C model files into the verilator work dir
|
cd $(SIM_VLT_DIR) && \
|
@echo; echo "\tLinking SystemC model source to verilator build path"; echo
|
|
@if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
|
|
@cd $(SIM_VLT_DIR) && \
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
if [ ! -e $$SYSCMODEL.cpp ]; then \
|
if [ ! -e $$SYSCMODEL.cpp ]; then \
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
|
fi; \
|
fi; \
|
done
|
done
|
# Now call verilator to generate the .mk's
|
|
cd $(SIM_VLT_DIR) && \
|
|
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
|
|
# Now call the first makefile it generated
|
|
cd $(SIM_VLT_DIR) && \
|
|
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
|
|
# Compile the module files
|
|
cd $(SIM_VLT_DIR) && \
|
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
|
done
|
|
cd $(SIM_VLT_DIR) && \
|
|
$(MAKE) -f Vorpsoc_top.mk verilated.o
|
|
# cd $(SIM_VLT_DIR) && \
|
|
# $(MAKE) -f Vorpsoc_top.mk SpTraceVcdC.o
|
|
# Now compile the top level systemC module
|
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
|
# Now archive all of the libraries from verilator witht he other modules we might have
|
|
cd $(SIM_VLT_DIR) && \
|
|
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
|
|
ar rcs libVorpsoc_top.a verilated.o; \
|
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
|
ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
|
|
done
|
|
# Final linking of the simulation executable. Order of libraries here is important!
|
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
|
|
|
|
################################################################################
|
# SystemC modules library
|
# Cleaning rules
|
$(SIM_VLT_DIR)/libmodules.a:
|
################################################################################
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
|
|
|
|
clean-sw:
|
clean-sw:
|
@for TEST in $(TESTS); do \
|
@for TEST in $(TESTS); do \
|
echo "Current test: $$TEST"; \
|
echo "Current test: $$TEST"; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
| Line 359... |
Line 388... |
done
|
done
|
$(MAKE) -C $(SW_DIR)/support clean
|
$(MAKE) -C $(SW_DIR)/support clean
|
$(MAKE) -C $(SW_DIR)/utils clean
|
$(MAKE) -C $(SW_DIR)/utils clean
|
|
|
clean-sim:
|
clean-sim:
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.*
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
