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Line 127... |
.PHONY: prepare_sw
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.PHONY: prepare_sw
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prepare_sw:
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prepare_sw:
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@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
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@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
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@$(MAKE) -C $(SW_DIR)/utils all
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@$(MAKE) -C $(SW_DIR)/utils all
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prepare_sw_uart_printf:
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@$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
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@$(MAKE) -C $(SW_DIR)/utils all
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# Rough guide to how these tests work:
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# Rough guide to how these tests work:
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# First, the couple of custom, required, software tools under sw/utils are
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# First, the couple of custom, required, software tools under sw/utils are
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# compiled, and then the software library files.
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# compiled, and then the software library files.
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# Next the few verilog files that need preperation are taken care of.
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# Next the few verilog files that need preperation are taken care of.
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Line 344... |
@cd $(SIM_VLT_DIR) && \
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@cd $(SIM_VLT_DIR) && \
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$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
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$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
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$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
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$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
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# Now call verilator to generate the .mk files
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# Now call verilator to generate the .mk files
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@echo; echo "\tCalling verilator"; echo
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@echo; echo "\tGenerating makefiles with Verilator"; echo
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cd $(SIM_VLT_DIR) && \
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cd $(SIM_VLT_DIR) && \
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verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
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verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
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# SystemC modules library
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# SystemC modules library
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$(SIM_VLT_DIR)/libmodules.a:
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$(SIM_VLT_DIR)/libmodules.a:
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Line 377... |
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
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ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
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ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
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ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
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fi; \
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fi; \
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done
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done
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################################################################################
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# Verilator test loop
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################################################################################
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# Verilator defaults to internal memories
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vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_vlt
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@echo
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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@for TEST in $(TESTS); do \
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echo "################################################################################"; \
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echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Compiling software ####"; echo; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
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rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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echo "\t#### Beginning simulation ####"; \
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time -p $(SIM_VLT_DIR)/Vorpsoc_top; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=1; \
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echo; echo "\t####"; \
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if [ $$TEST_RESULT -gt 0 ]; then \
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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else echo "\t#### Test $$TEST FAILED ####";\
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fi; \
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echo "\t####"; echo; \
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TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
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done; \
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echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
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################################################################################
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################################################################################
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# Cleaning rules
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# Cleaning rules
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################################################################################
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################################################################################
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clean-sw:
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clean-sw:
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