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#### Public License along with this source; if not, download it ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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# Use: Type "make rtl-tests" to run all of the tests on the RTL model
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# Usage:
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# run in the Icarus Verilog simulator.
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#
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# make rtl-tests
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# The results and output of the simulation are in the results path,
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#
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# in parallel to the simulation run and bin paths. This directory is
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# Run the software tests in the RTL model of the ORPSoC being
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# not checked into the repository, but is created when simulations are
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# simulated with an event-driven simulator like Icarus. Also
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# run.
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# possible to use Cadence's Verilog simulators with the
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# "rtl-nc-tests" target.
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#
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# make vlt-tests
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#
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# Run all the software tests in the RTL model which has been
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# converted into a cycle-accurate SystemC model with Verilator.
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#
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# Simulation results:
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#
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# The results and output of the event-driven simulations are in the
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# results path, in parallel to the simulation run and bin paths.
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# Specific tests:
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#
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# To run an individual test, specify it in the variable TESTS when
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# To run an individual test, specify it in the variable TESTS when
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# calling make, like "make rtl-tests TESTS="mmu-nocache mul-idcd-O2".
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# calling make, eg:
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#
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# make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
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# UART printf:
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#
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# It is possible to enable printf to the console via the UART when
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# running the event-driven simulators. To do this define UART_PRINTF=1
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# when calling make. The SystemC cycle-acccurate model uses this by
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# default.
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# VCDs:
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#
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# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# to inspect the internals of the system graphically) files can be
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# to inspect the internals of the system graphically) files can be
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# generated by calling the make with VCD=1, like "make rtl-tests VCD=1"
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# generated by defining a variable VCD, eg.
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# and a vcd file will be created in the simulation results directory,
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#
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# and named according to the test run which generated it.
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# make rtl-tests VCD=1
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#
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# and a dump file will be created in the simulation results directory,
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# and named according to the test run which generated it. This is
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# possible for both event-driven and cycle-accurate simulations.
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# However the cycle-accurate
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# The rtl simulations can also be run with Cadences NCSim by using
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# The rtl simulations can also be run with Cadences NCSim by using
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# rtl-nc-tests in the place of rtl-tests.
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# rtl-nc-tests in the place of rtl-tests.
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# It is possible to speed up the simulation slightly by disabling
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# It is possible to speed up the simulation slightly by disabling
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Line 328... |
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# List of System C models - use this list to link the sources into the Verilator
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# List of System C models - use this list to link the sources into the Verilator
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# build directory
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# build directory
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SYSC_MODELS=OrpsocAccess TraceSC
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SYSC_MODELS=OrpsocAccess TraceSC
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ifdef VCD
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VLT_FLAGS +=-trace
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endif
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# Only need the trace target if we are tracing
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# Only need the trace target if we are tracing
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ifneq (,$(findstring -trace, $(VLT_FLAGS)))
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ifneq (,$(findstring -trace, $(VLT_FLAGS)))
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VLT_TRACEOBJ = SpTraceVcdC
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VLT_TRACEOBJ = SpTraceVcdC
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endif
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endif
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
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rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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echo "\t#### Beginning simulation ####"; \
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echo "\t#### Beginning simulation ####"; \
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time -p $(SIM_VLT_DIR)/Vorpsoc_top; \
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time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=1; \
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TEST_RESULT=1; \
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echo; echo "\t####"; \
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echo; echo "\t####"; \
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if [ $$TEST_RESULT -gt 0 ]; then \
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if [ $$TEST_RESULT -gt 0 ]; then \
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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