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#### ORPSoCv2 Testbenches Makefile ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ####
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#### ####
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#### Description ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### configuring and running different tests on the current ####
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#### ORPSoC design. ####
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#### ORPSoC(v2) design. ####
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#### ####
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#### ####
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#### To Do: ####
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#### To Do: ####
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#### - Verilator tests ####
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#### * Arrange verilator make rules so that the whole thing ####
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#### isn't recompiled when a single SystemC module is ####
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#### updated. ####
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#### * Test if each software test file gets made properly ####
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#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####
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#### ####
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#### ####
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#### Author(s): ####
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#### Author(s): ####
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#### - jb, jb@orsoc.se ####
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#### - jb, jb@orsoc.se ####
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#### ####
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#### ####
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#### ####
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#### ####
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# make vlt-tests
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# make vlt-tests
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#
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#
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# Run all the software tests in the RTL model which has been
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# Run all the software tests in the RTL model which has been
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# converted into a cycle-accurate SystemC model with Verilator.
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# converted into a cycle-accurate SystemC model with Verilator.
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#
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#
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# make sim-tests
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#
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# Run all the software tests in the architectural simulator
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#
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# Simulation results:
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# Simulation results:
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#
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#
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# The results and output of the event-driven simulations are in the
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# The results and output of the event-driven simulations are in the
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# results path, in parallel to the simulation run and bin paths.
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# results path, in parallel to the simulation run and bin paths.
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#
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#
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# It is possible to enable printf to the console via the UART when
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# It is possible to enable printf to the console via the UART when
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# running the event-driven simulators. To do this define UART_PRINTF=1
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# running the event-driven simulators. To do this define UART_PRINTF=1
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# when calling make. The SystemC cycle-acccurate model uses this by
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# when calling make. The SystemC cycle-acccurate model uses this by
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# default.
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# default.
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# Also note when switching between runs with and without UART printf
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# enabled, run a clean-sw so the library files are recompiled when
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# the tests are run - this is not done automatically.
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# VCDs:
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# VCDs:
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#
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#
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# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# to inspect the internals of the system graphically) files can be
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# to inspect the internals of the system graphically) files can be
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# and a dump file will be created in the simulation results directory,
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# and a dump file will be created in the simulation results directory,
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# and named according to the test run which generated it. This is
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# and named according to the test run which generated it. This is
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# possible for both event-driven and cycle-accurate simulations.
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# possible for both event-driven and cycle-accurate simulations.
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# However the cycle-accurate
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# However the cycle-accurate
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# The rtl simulations can also be run with Cadences NCSim by using
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# NO_SIM_LOGGING:
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# rtl-nc-tests in the place of rtl-tests.
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#
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# It is possible to speed up the event-driven simulation slightly by
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# disabling log output of the processor's state to files by defining
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# NO_SIM_LOGGING, eg:
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#
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# make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
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#
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# It is possible to speed up the simulation slightly by disabling
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# Cleaning:
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# log output of the processor's state to files by defining
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# A simple "make clean" cleans everything - software and all temporary
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# NO_SIM_LOGGING, eg. make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
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# simulation files and directories. To clean just the software run:
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#
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# make clean-sw
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#
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# and to clean just the temporary simulation files (including VCDs,
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# results logs - everything under, and including, sim/results/, run
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#
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# make clean-sim
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#
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# Note:
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#
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# The way each of the test loops is written is probably a bit overly complex
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# but this is to save maintaining and calling other files to get this done.
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#
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# Name of the directory we're currently in
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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# The root path of the whole project
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# The root path of the whole project
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################################################################################
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################################################################################
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# Cleaning rules
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# Cleaning rules
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################################################################################
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################################################################################
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clean: clean-sw clean-sim
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clean-sw:
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clean-sw:
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@for TEST in $(TESTS); do \
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@for TEST in $(TESTS); do \
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echo "Current test: $$TEST"; \
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echo "Current test: $$TEST"; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
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echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
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