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#### Description ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### configuring and running different tests on the current ####
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#### ORPSoC(v2) design. ####
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#### ORPSoC(v2) design. ####
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#### ####
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#### ####
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#### To Do: ####
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#### To do: ####
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#### * Arrange verilator make rules so that the whole thing ####
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#### * Arrange verilator make rules so that the whole thing ####
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#### isn't recompiled when a single SystemC module is ####
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#### isn't recompiled when a single SystemC module is ####
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#### updated. ####
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#### updated. ####
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#### * Test if each software test file gets made properly ####
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#### * Test if each software test file gets made properly ####
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#### before it's run in whatever model we're using ####
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#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####
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#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####
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#### ####
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#### ####
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#### Author(s): ####
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#### Author(s): ####
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#### - jb, jb@orsoc.se ####
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#### - jb, jb@orsoc.se ####
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#### ####
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#### ####
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#
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#
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# Note:
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# Note:
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#
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#
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# The way each of the test loops is written is probably a bit overly complex
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# The way each of the test loops is written is probably a bit overly complex
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# but this is to save maintaining and calling other files to get this done.
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# but this is to save maintaining, and calling, multiple files.
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#
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#
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# Name of the directory we're currently in
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# Model configuration:
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#
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# Currently, the ORPSoCv2, by default, contains an internal SRAM (configurable
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# size - check the defparam in rtl/verilog/orpsoc_top.v), standard OR1200 (check
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# the config in rtl/verilog/or1200_defines.v) and UART.
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# Switches can be passed to enable certain parts of the design if testing with
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# these is desired.
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#
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# SDRAM and controller
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#
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# To enable the use of SDRAM, define USE_SDRAM when calling the sim -this
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# only has an effect in the event-driven simulators as the external SDRAM model
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# is not availble in SystemC format. eg:
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#
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# make rtl-tests USE_SDRAM=1
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#
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# This not only enables SDRAM but also enables the booting from external SPI
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# interfaced flash memory. This causes significant increase in the time taken
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# for simulation as the program to test is first loaded out of SPI flash memory
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# and into SDRAM before it is executed. Although this more closely mimics the
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# behaviour of the hardware, for simulation purposes it is purely time-consuming
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# however it may be useful to track down any problems with this boot-loading
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# process. Therefore, becuase it enables SDRAM memory, ir also enables the flash
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# memory model and SPI controller inside ORPSoC.
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#
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# Ethernet
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#
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# Ethernet is disabled by default. This is due to the fact that it is not
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# supported in the verilator/systemC model. Also, there is currently no software
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# which tests it in any meaningful way.
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#
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#
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# Event-driven simulation compilation
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#
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# The way the event-driven simulations are compiled is simply using the
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# configuration script file in this directory, currently called icarus.scr -
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# however it is first processesed to replace the variables, beginning with $'s,
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# with the appropriate paths. Instead of naming each file to be compiled, the
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# paths to be searched for each module are instead defined ( -y paths), and
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# only the toplevel testbench and library source files are explicitly named.
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# This simplifies the script, and also requires that the name of each verilog
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# source file is the same as the module it contains (a good convention
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# regardless.) In addition to the script/command file, defines are passed to
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# the compiler via the command line in the EVENT_SIM_FLAGS variable.
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# Additionally, a source file, test_define.v, is created with some defines
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# that cannot be passed to the compiled reliably (there are differences between
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# the way, for instance, icarus and ncverilog parse strings +define+'d on the
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# command line). This file is then included at the appropriate places.
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# It is probably not ideal that the entire design be re-compiled for each test,
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# but currently the design is small enough so that this doesn't cause a
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# significant overhead, unlike the cycle-accurate model compile time.
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#
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#
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# SystemC cycle-accurate model compilation
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#
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# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
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# behind this is verilator, which processes the RTL sources and generates a c++
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# description of the system. This c++ description is then compiled with a
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# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
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# model, as well as any other modules - in this case a reset generation, UART
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# decoder, and monitor module are included at the top level. These additional
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# modules and models are written in SystemC and compiled all together with the
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# cycle-accurate ORPSoC model to create the simulation executable. Finally this
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# executable is run and should be a cycle-representation of the system. VCDs
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# can be generated if enabled. The compiled mentioned above is all done with
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# the GNU c++ compiler, g++.
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# The compilation process is a little more tricky than a typical even-driven
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# simulator. It proceeds basically by generating the makefiles for compiling
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# the design with verilator, running these makes which produces a library
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# containing the cycle-accurate ORPSoC design, compiling the additional
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# top-level, and testbench, systemC models into a library, and then linking it
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# all together into the simulation executable.
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# The major advantage of the cycle-accurate model is that it is quicker, in
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# terms of simulated cycles/second, when compared with event-driven simulators.
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# It is, of course, less accurate in that it cannot model propegation delays.
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# However this is usually not an issue for simulating a design which is known
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# to synthesize and run OK. It is very useful for running complex software,
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# such as the linux kernel and real-time OS applications, which generally
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# require long simulation times.
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# Currently the cycle-accurate model being used doesn't contain much more than
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# the processor and a UART, however it's exepected in future this will be
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# expanded on and more complex software test suites will be implemented to put
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# the system through its paces.
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#
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# Name of
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# the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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# The root path of the whole project
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# The root path of the whole project
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PROJECT_ROOT=$(CUR_DIR)/../..
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PROJECT_ROOT=$(CUR_DIR)/../..
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Line 252... |
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# If USE_SDRAM is defined we'll add it to the simulator's defines on the
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# If USE_SDRAM is defined we'll add it to the simulator's defines on the
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# command line becuase it's used by many different modules and it's easier
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# command line becuase it's used by many different modules and it's easier
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# to do it this way than make them all include a file.
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# to do it this way than make them all include a file.
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ifdef USE_SDRAM
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ifdef USE_SDRAM
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RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
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EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
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endif
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endif
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SIM_FLASH_MEM_FILE="flash.in"
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SIM_FLASH_MEM_FILE="flash.in"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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SIM_SRAM_MEM_FILE="sram.vmem"
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SIM_SRAM_MEM_FILE="sram.vmem"
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Line 367... |
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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fi; \
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echo ; \
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echo ; \
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echo "\t#### Compiling RTL ####"; \
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echo "\t#### Compiling RTL ####"; \
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rm -f $(SIM_RUN_DIR)/a.out; \
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rm -f $(SIM_RUN_DIR)/a.out; \
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$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
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$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS); \
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echo; \
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echo; \
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echo "\t#### Beginning simulation ####"; \
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echo "\t#### Beginning simulation ####"; \
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time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
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time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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Line 427... |
if [ -z $$NO_SIM_LOGGING ]; then \
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if [ -z $$NO_SIM_LOGGING ]; then \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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fi; \
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echo ; \
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echo ; \
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echo "\t#### Beginning simulation ####"; \
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echo "\t#### Beginning simulation ####"; \
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time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
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time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(EVENT_SIM_FLAGS); \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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echo; echo "\t####"; \
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echo; echo "\t####"; \
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if [ $$TEST_RESULT -gt 0 ]; then \
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if [ $$TEST_RESULT -gt 0 ]; then \
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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