| Line 39... |
Line 39... |
$RTL_DIR/components/uart16550/uart_top.v
|
$RTL_DIR/components/uart16550/uart_top.v
|
$RTL_DIR/components/uart16550/uart_transmitter.v
|
$RTL_DIR/components/uart16550/uart_transmitter.v
|
$RTL_DIR/components/uart16550/uart_sync_flops.v
|
$RTL_DIR/components/uart16550/uart_sync_flops.v
|
$RTL_DIR/components/uart16550/uart_receiver.v
|
$RTL_DIR/components/uart16550/uart_receiver.v
|
$RTL_DIR/components/uart16550/uart_wb.v
|
$RTL_DIR/components/uart16550/uart_wb.v
|
$RTL_DIR/components/uart16550/timescale.v
|
//$RTL_DIR/components/uart16550/timescale.v
|
|
|
// Ethernet MAC
|
// Ethernet MAC
|
$RTL_DIR/eth_defines.v
|
$RTL_DIR/eth_defines.v
|
$RTL_DIR/components/ethernet/eth_registers.v
|
$RTL_DIR/components/ethernet/eth_registers.v
|
$RTL_DIR/components/ethernet/eth_maccontrol.v
|
$RTL_DIR/components/ethernet/eth_maccontrol.v
|
| Line 69... |
Line 69... |
$RTL_DIR/components/ethernet/eth_shiftreg.v
|
$RTL_DIR/components/ethernet/eth_shiftreg.v
|
$RTL_DIR/components/ethernet/eth_receivecontrol.v
|
$RTL_DIR/components/ethernet/eth_receivecontrol.v
|
$RTL_DIR/components/ethernet/eth_txethmac.v
|
$RTL_DIR/components/ethernet/eth_txethmac.v
|
$RTL_DIR/components/ethernet/eth_random.v
|
$RTL_DIR/components/ethernet/eth_random.v
|
$RTL_DIR/components/ethernet/eth_register.v
|
$RTL_DIR/components/ethernet/eth_register.v
|
$RTL_DIR/components/ethernet/timescale.v
|
//$RTL_DIR/components/ethernet/timescale.v
|
|
|
// SDRAM controller
|
// SDRAM controller
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_defines.v
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_defines.v
|
$RTL_DIR/components/wb_sdram_ctrl/delay.v
|
$RTL_DIR/components/wb_sdram_ctrl/delay.v
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
$RTL_DIR/components/wb_sdram_ctrl/fifo.v
|
$RTL_DIR/components/wb_sdram_ctrl/fifo.v
|
|
|
// OR1200
|
// OR1200
|
$RTL_DIR/or1200_defines.v
|
|
$RTL_DIR/components/or1200r2/or1200_spram_256x21.v
|
$RTL_DIR/components/or1200r2/or1200_spram_256x21.v
|
$RTL_DIR/components/or1200r2/or1200_dpram_256x32.v
|
$RTL_DIR/components/or1200r2/or1200_dpram_256x32.v
|
$RTL_DIR/components/or1200r2/or1200_xcv_ram32x8d.v
|
$RTL_DIR/components/or1200r2/or1200_xcv_ram32x8d.v
|
$RTL_DIR/components/or1200r2/or1200_ic_top.v
|
$RTL_DIR/components/or1200r2/or1200_ic_top.v
|
$RTL_DIR/components/or1200r2/or1200_ic_fsm.v
|
$RTL_DIR/components/or1200r2/or1200_ic_fsm.v
|
| Line 121... |
Line 120... |
$RTL_DIR/components/or1200r2/or1200_spram_2048x32.v
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x32.v
|
$RTL_DIR/components/or1200r2/or1200_genpc.v
|
$RTL_DIR/components/or1200r2/or1200_genpc.v
|
$RTL_DIR/components/or1200r2/or1200_spram_128x32.v
|
$RTL_DIR/components/or1200r2/or1200_spram_128x32.v
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x8.v
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x8.v
|
$RTL_DIR/components/or1200r2/or1200_spram_64x14.v
|
$RTL_DIR/components/or1200r2/or1200_spram_64x14.v
|
$RTL_DIR/components/or1200r2/or1200_defines.v
|
//$RTL_DIR/components/or1200r2/or1200_defines.v
|
$RTL_DIR/components/or1200r2/or1200_top.v
|
$RTL_DIR/components/or1200r2/or1200_top.v
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x32.v
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x32.v
|
$RTL_DIR/components/or1200r2/or1200_rfram_generic.v
|
$RTL_DIR/components/or1200r2/or1200_rfram_generic.v
|
$RTL_DIR/components/or1200r2/or1200_except.v
|
$RTL_DIR/components/or1200r2/or1200_except.v
|
$RTL_DIR/components/or1200r2/or1200_operandmuxes.v
|
$RTL_DIR/components/or1200r2/or1200_operandmuxes.v
|
| Line 141... |
Line 140... |
$RTL_DIR/components/or1200r2/or1200_dpram_32x32.v
|
$RTL_DIR/components/or1200r2/or1200_dpram_32x32.v
|
$RTL_DIR/components/or1200r2/or1200_tt.v
|
$RTL_DIR/components/or1200r2/or1200_tt.v
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x32_bw.v
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x32_bw.v
|
$RTL_DIR/components/or1200r2/or1200_spram_64x22.v
|
$RTL_DIR/components/or1200r2/or1200_spram_64x22.v
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x8.v
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x8.v
|
$RTL_DIR/components/or1200r2/timescale.v
|
//$RTL_DIR/components/or1200r2/timescale.v
|
$RTL_DIR/components/or1k_startup/copyright_OR1K_startup.v
|
$RTL_DIR/components/or1k_startup/copyright_OR1K_startup.v
|
$RTL_DIR/components/or1k_startup/spi_shift.v
|
$RTL_DIR/components/or1k_startup/spi_shift.v
|
$RTL_DIR/components/or1k_startup/OR1K_startup_generic.v
|
$RTL_DIR/components/or1k_startup/OR1K_startup_generic.v
|
$RTL_DIR/components/or1k_startup/copyright_spi.v
|
$RTL_DIR/components/or1k_startup/copyright_spi.v
|
//$RTL_DIR/components/or1k_startup/OR1K_startup.v
|
//$RTL_DIR/components/or1k_startup/OR1K_startup.v
|
| Line 155... |
Line 154... |
//$RTL_DIR/components/or1k_startup/flash_wb_32x32.v
|
//$RTL_DIR/components/or1k_startup/flash_wb_32x32.v
|
$RTL_DIR/components/or1k_startup/spi_top.v
|
$RTL_DIR/components/or1k_startup/spi_top.v
|
$RTL_DIR/components/or1k_startup/spi_clgen.v
|
$RTL_DIR/components/or1k_startup/spi_clgen.v
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_ACTEL.v
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_ACTEL.v
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_ACTEL_IP.v
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_ACTEL_IP.v
|
$RTL_DIR/components/or1k_startup/timescale.v
|
//$RTL_DIR/components/or1k_startup/timescale.v
|
$RTL_DIR/components/or1k_top/or1k_top.v
|
$RTL_DIR/components/or1k_top/or1k_top.v
|
|
|
|
|
// JTAG TAP
|
// JTAG TAP
|
$RTL_DIR/components/tap/tap_defines.v
|
$RTL_DIR/components/tap/tap_defines.v
|
//$RTL_DIR/components/tap/tap.v
|
//$RTL_DIR/components/tap/tap.v
|
$RTL_DIR/components/tap/tap_top.v
|
$RTL_DIR/components/tap/tap_top.v
|
$RTL_DIR/components/tap/timescale.v
|
//$RTL_DIR/components/tap/timescale.v
|
|
|
|
|
$RTL_DIR/components/smii/smii_sync.v
|
$RTL_DIR/components/smii/smii_sync.v
|
$RTL_DIR/components/smii/copyright.v
|
$RTL_DIR/components/smii/copyright.v
|
$RTL_DIR/components/smii/generic_buffers.v
|
$RTL_DIR/components/smii/generic_buffers.v
|
| Line 185... |
Line 184... |
$RTL_DIR/components/debug_if/dbg_top.v
|
$RTL_DIR/components/debug_if/dbg_top.v
|
$RTL_DIR/components/debug_if/dbg_crc32_d1.v
|
$RTL_DIR/components/debug_if/dbg_crc32_d1.v
|
$RTL_DIR/components/debug_if/dbg_defines_old.v
|
$RTL_DIR/components/debug_if/dbg_defines_old.v
|
$RTL_DIR/components/debug_if/dbg_wb_defines.v
|
$RTL_DIR/components/debug_if/dbg_wb_defines.v
|
$RTL_DIR/components/debug_if/dbg_defines.v
|
$RTL_DIR/components/debug_if/dbg_defines.v
|
$RTL_DIR/components/debug_if/timescale.v
|
//$RTL_DIR/components/debug_if/timescale.v
|
|
|
No newline at end of file
|
No newline at end of file
|
