URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sim/] [bin/] [verilator.scr] - Diff between revs 44 and 47

Rev 44	Rev 47
Line 1...	Line 1...
`// This file should be processed by the Makefile before being used`	`// This file should be processed by the Makefile before being used`
`+incdir+$BENCH_DIR`	`+incdir+$BENCH_DIR`
	`+incdir+$BENCH_DIR/../sysc/include`
`+incdir+$BACKEND_DIR`	`+incdir+$BACKEND_DIR`
`+incdir+$RTL_DIR`	`+incdir+$RTL_DIR`
`+incdir+$RTL_DIR/components/uart16550`	`+incdir+$RTL_DIR/components/uart16550`
`+incdir+$RTL_DIR/components/ethernet`	`+incdir+$RTL_DIR/components/ethernet`
`+incdir+$RTL_DIR/components/or1k_startup`	`+incdir+$RTL_DIR/components/or1k_startup`
Line 22...	Line 23...
`-y $RTL_DIR/components/or1200r2`	`-y $RTL_DIR/components/or1200r2`
`-y $RTL_DIR/components/tap`	`-y $RTL_DIR/components/tap`
`-y $RTL_DIR/components/smii`	`-y $RTL_DIR/components/smii`
`-y $RTL_DIR/components/debug_if`	`-y $RTL_DIR/components/debug_if`
`-y $RTL_DIR/components/wb_sdram_ctrl`	`-y $RTL_DIR/components/wb_sdram_ctrl`
	`-y $RTL_DIR/components/ram_wb`

`// RTL files (top)`	`// RTL files (top)`
`$RTL_DIR/orpsoc_top.v`	`$RTL_DIR/orpsoc_top.v`

`-v $RTL_DIR/components/smii/generic_buffers.v`	`-v $RTL_DIR/components/smii/generic_buffers.v`
`-v $BACKEND_DIR/sim_lib.v`	`-v $BACKEND_DIR/sim_lib.v`

	`+define+DISABLE_IOS_FOR_VERILATOR`

`No newline at end of file`	`No newline at end of file`