| Line 42... |
Line 42... |
l.addi r28,r0,0x0
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l.addi r28,r0,0x0
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l.addi r29,r0,0x0
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l.addi r29,r0,0x0
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l.addi r30,r0,0x0
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l.addi r30,r0,0x0
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l.addi r31,r0,0x0
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l.addi r31,r0,0x0
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! l.movhi r3,hi(MC_BASE_ADDR)
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/*
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! l.ori r3,r3,MC_BA_MASK
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l.movhi r3,hi(MC_BASE_ADDR)
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! l.addi r5,r0,0x00
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l.ori r3,r3,MC_BA_MASK
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! l.sw 0(r3),r5
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l.addi r5,r0,0x00
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l.sw 0(r3),r5
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*/
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l.movhi r3,hi(_start)
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l.movhi r3,hi(_start)
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l.ori r3,r3,lo(_start)
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l.ori r3,r3,lo(_start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.section .text
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.section .text
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_start:
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_start:
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l.jal _init_mc
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l.nop
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.if IC | DC
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.if IC | DC
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/* Flush IC and/or DC */
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/* Flush IC and/or DC */
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l.addi r10,r0,0
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l.addi r10,r0,0
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l.addi r11,r0,0
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l.addi r11,r0,0
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| Line 99... |
Line 99... |
l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.endif
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.endif
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|
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/* Wait for SDRAM */
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l.addi r3,r0,0x1 /* 0x1000 */
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1: l.sfeqi r3,0
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l.bnf 1b
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l.addi r3,r3,-1
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|
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/* Copy from flash to sram */
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l.movhi r3,hi(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.movhi r4,hi(_icm_start)
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l.ori r4,r4,lo(_icm_start)
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l.movhi r5,hi(_icm_end)
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l.ori r5,r5,lo(_icm_end)
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l.sub r5,r5,r4
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l.sfeqi r5,0
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l.bf 20f
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l.nop
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10: l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.bf 10b
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l.nop
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20:
|
|
|
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/* Copy from flash to sram */
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l.movhi r3,hi(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.movhi r4,hi(_vec_start)
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l.ori r4,r4,lo(_vec_start)
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l.movhi r5,hi(_vec_end)
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l.ori r5,r5,lo(_vec_end)
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l.sub r5,r5,r4
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l.sfeqi r5,0
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l.bf 2f
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l.nop
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1: l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.bf 1b
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l.nop
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2:
|
|
l.movhi r4,hi(_dst_beg)
|
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l.ori r4,r4,lo(_dst_beg)
|
|
l.movhi r5,hi(_dst_end)
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l.ori r5,r5,lo(_dst_end)
|
|
1: l.sfgeu r4,r5
|
|
l.bf 1f
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l.nop
|
|
l.lwz r8,0(r3)
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|
l.sw 0(r4),r8
|
|
l.addi r3,r3,4
|
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l.bnf 1b
|
|
l.addi r4,r4,4
|
|
1:
|
|
l.addi r3,r0,0
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l.addi r4,r0,0
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|
3:
|
|
/* Set stack pointer */
|
/* Set stack pointer */
|
l.movhi r1,hi(_stack)
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l.movhi r1,hi(_stack)
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l.ori r1,r1,lo(_stack)
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l.ori r1,r1,lo(_stack)
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|
|
/* Jump to main */
|
/* Jump to main */
|
l.movhi r2,hi(_reset)
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l.movhi r2,hi(_reset)
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l.ori r2,r2,lo(_reset)
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l.ori r2,r2,lo(_reset)
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l.jr r2
|
l.jr r2
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l.nop
|
l.nop
|
|
|
_init_mc:
|
|
|
|
l.movhi r3,hi(MC_BASE_ADDR)
|
|
l.ori r3,r3,lo(MC_BASE_ADDR)
|
|
|
|
l.addi r4,r3,MC_CSC(0)
|
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l.movhi r5,hi(FLASH_BASE_ADDR)
|
|
l.srai r5,r5,6
|
|
l.ori r5,r5,0x0025
|
|
l.sw 0(r4),r5
|
|
|
|
l.addi r4,r3,MC_TMS(0)
|
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l.movhi r5,hi(FLASH_TMS_VAL)
|
|
l.ori r5,r5,lo(FLASH_TMS_VAL)
|
|
l.sw 0(r4),r5
|
|
|
|
l.addi r4,r3,MC_BA_MASK
|
|
l.addi r5,r0,MC_MASK_VAL
|
|
l.sw 0(r4),r5
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|
|
|
l.addi r4,r3,MC_CSR
|
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l.movhi r5,hi(MC_CSR_VAL)
|
|
l.ori r5,r5,lo(MC_CSR_VAL)
|
|
l.sw 0(r4),r5
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|
|
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l.addi r4,r3,MC_TMS(1)
|
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l.movhi r5,hi(SDRAM_TMS_VAL)
|
|
l.ori r5,r5,lo(SDRAM_TMS_VAL)
|
|
l.sw 0(r4),r5
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|
|
|
l.addi r4,r3,MC_CSC(1)
|
|
l.movhi r5,hi(SDRAM_BASE_ADDR)
|
|
l.srai r5,r5,6
|
|
l.ori r5,r5,0x0411
|
|
l.sw 0(r4),r5
|
|
|
|
l.addi r4,r3,MC_TMS(2)
|
|
l.movhi r5,hi(SDRAM_TMS_VAL)
|
|
l.ori r5,r5,lo(SDRAM_TMS_VAL)
|
|
l.sw 0(r4),r5
|
|
|
|
l.addi r4,r3,MC_CSC(2)
|
|
l.movhi r5,hi(0x00800000)
|
|
l.srai r5,r5,6
|
|
l.ori r5,r5,0x0411
|
|
l.sw 0(r4),r5
|
|
|
|
l.jr r9
|
|
l.nop
|
|
|
|
