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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- --
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-- This is the 68000 software compatible Kernal of TG68 --
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-- This is the 68000 software compatible Kernal of TG68 --
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-- --
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-- --
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-- Copyright (c) 2007 Tobias Gubener <tobiflex@opencores.org> --
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-- Copyright (c) 2007-2010 Tobias Gubener <tobiflex@opencores.org> --
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-- --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published --
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-- it under the terms of the GNU Lesser General Public License as published --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- (at your option) any later version. --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- Revision 1.08 2010/06/14
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-- Bugfix Movem with regmask==xFFFF
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-- Add missing Illegal $4AFC
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--
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-- Revision 1.07 2009/10/02
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-- Bugfix Movem with regmask==x0000
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--
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-- Revision 1.06 2009/02/10
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-- Revision 1.06 2009/02/10
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-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
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-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
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-- Example lsr.l D2,D2
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-- Example lsr.l D2,D2
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-- Thanks to Peter Graf for report
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-- Thanks to Peter Graf for report
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--
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--
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-- Add CHK INSTRUCTION
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-- Add CHK INSTRUCTION
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-- full decode ILLEGAL INSTRUCTIONS
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-- full decode ILLEGAL INSTRUCTIONS
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-- Add FC Output
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-- Add FC Output
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-- add odd Address test
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-- add odd Address test
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-- add TRACE
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-- add TRACE
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-- Movem with regmask==x0000
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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signal movem_addr : std_logic;
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signal movem_addr : std_logic;
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signal movem_regaddr : std_logic_vector(3 downto 0);
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signal movem_regaddr : std_logic_vector(3 downto 0);
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signal movem_mask : std_logic_vector(15 downto 0);
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signal movem_mask : std_logic_vector(15 downto 0);
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signal set_get_movem_mask : std_logic;
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signal set_get_movem_mask : std_logic;
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signal get_movem_mask : std_logic;
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signal get_movem_mask : std_logic;
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signal maskzero : std_logic;
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signal test_maskzero : std_logic;
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signal movem_muxa : std_logic_vector(7 downto 0);
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signal movem_muxa : std_logic_vector(7 downto 0);
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signal movem_muxb : std_logic_vector(3 downto 0);
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signal movem_muxb : std_logic_vector(3 downto 0);
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signal movem_muxc : std_logic_vector(1 downto 0);
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signal movem_muxc : std_logic_vector(1 downto 0);
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signal movem_presub : std_logic;
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signal movem_presub : std_logic;
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signal save_memaddr : std_logic;
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signal save_memaddr : std_logic;
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Line 656... |
rot_cnt <="000001";
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rot_cnt <="000001";
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rot_nop <= '0';
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rot_nop <= '0';
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get_extendedOPC <= '0';
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get_extendedOPC <= '0';
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get_bitnumber <= '0';
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get_bitnumber <= '0';
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get_movem_mask <= '0';
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get_movem_mask <= '0';
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test_maskzero <= '0';
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movepl <= '0';
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movepl <= '0';
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movepw <= '0';
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movepw <= '0';
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test_delay <= "000";
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test_delay <= "000";
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PCmarker <= '0';
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PCmarker <= '0';
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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IF clkena_in='1' THEN
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IF clkena_in='1' THEN
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get_extendedOPC <= set_get_extendedOPC;
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get_extendedOPC <= set_get_extendedOPC;
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get_bitnumber <= set_get_bitnumber;
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get_bitnumber <= set_get_bitnumber;
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get_movem_mask <= set_get_movem_mask;
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get_movem_mask <= set_get_movem_mask;
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test_maskzero <= get_movem_mask;
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setstate_delay <= setstate;
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setstate_delay <= setstate;
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TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
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TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
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IF directPC='1' AND clkena='1' THEN
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IF directPC='1' AND clkena='1' THEN
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TG68_PC <= data_read;
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TG68_PC <= data_read;
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Line 1013... |
END PROCESS;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Write Reg
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-- Write Reg
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA)
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PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
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BEGIN
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BEGIN
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Lwrena <= '0';
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Lwrena <= '0';
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Hwrena <= '0';
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Hwrena <= '0';
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registerin <= OP1in;
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registerin <= OP1in;
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IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
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IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
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Hwrena <= '1';
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Hwrena <= '1';
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Lwrena <= '1';
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Lwrena <= '1';
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ELSIF Regwrena='1' THEN --read (mem)
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ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
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Lwrena <= '1';
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Lwrena <= '1';
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CASE datatype IS
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CASE datatype IS
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WHEN "00" => --BYTE
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WHEN "00" => --BYTE
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registerin(15 downto 8) <= reg_QA(15 downto 8);
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registerin(15 downto 8) <= reg_QA(15 downto 8);
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WHEN "01" => --WORD
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WHEN "01" => --WORD
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END PROCESS;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- execute opcode
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-- execute opcode
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
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PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
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Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
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Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
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Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
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Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
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BEGIN
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BEGIN
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TG68_PC_br8 <= '0';
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TG68_PC_br8 <= '0';
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TG68_PC_brw <= '0';
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TG68_PC_brw <= '0';
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Line 1875... |
END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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WHEN "101"=> --tst, tas
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WHEN "101"=> --tst, tas
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IF opcode(7 downto 2)="111111" THEN --4AFC illegal
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trap_illegal <= '1';
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trapmake <= '1';
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ELSE
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IF decodeOPC='1' THEN
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IF decodeOPC='1' THEN
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ea_build <= '1';
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ea_build <= '1';
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END IF;
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END IF;
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IF execOPC='1' THEN
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IF execOPC='1' THEN
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dest_hbits <= '1'; --for Flags
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dest_hbits <= '1'; --for Flags
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Line 1898... |
datatype <= "00"; --Byte
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datatype <= "00"; --Byte
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IF execOPC='1' AND endOPC='1' THEN
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IF execOPC='1' AND endOPC='1' THEN
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regwrena <= '1';
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regwrena <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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-- WHEN "110"=>
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-- WHEN "110"=>
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WHEN "111"=> --4EXX
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WHEN "111"=> --4EXX
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IF opcode(7)='1' THEN --jsr, jmp
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IF opcode(7)='1' THEN --jsr, jmp
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datatype <= "10";
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datatype <= "10";
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ea_only <= '1';
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ea_only <= '1';
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Line 3198... |
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
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("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
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IF reset = '0' THEN
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IF reset = '0' THEN
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movem_busy <= '0';
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movem_busy <= '0';
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movem_addr <= '0';
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movem_addr <= '0';
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maskzero <= '0';
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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IF clkena_in='1' AND get_movem_mask='1' THEN
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IF clkena_in='1' AND get_movem_mask='1' THEN
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movem_mask <= data_read(15 downto 0);
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movem_mask <= data_read(15 downto 0);
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END IF;
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END IF;
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IF clkena_in='1' AND test_maskzero='1' THEN
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IF movem_mask=X"0000" THEN
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maskzero <= '1';
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END IF;
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END IF;
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IF clkena_in='1' AND endOPC='1' THEN
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maskzero <= '0';
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END IF;
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IF clkena='1' THEN
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IF clkena='1' THEN
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IF set_movem_busy='1' THEN
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IF set_movem_busy='1' THEN
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IF movem_bits(3 downto 1) /= "000" OR opcode(10)='0' THEN
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IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
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movem_busy <= '1';
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movem_busy <= '1';
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END IF;
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END IF;
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movem_addr <= '1';
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movem_addr <= '1';
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END IF;
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END IF;
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IF movem_addr='1' THEN
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IF movem_addr='1' THEN
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