| Line 19... |
Line 19... |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
-- --
|
-- --
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--
|
--
|
|
--
|
|
-- Revision 1.01 2007/11/28
|
|
-- add MOVEP
|
|
-- Bugfix Interrupt in MOVEQ
|
|
--
|
-- Revision 1.0 2007/11/05
|
-- Revision 1.0 2007/11/05
|
-- Clean up code and first release
|
-- Clean up code and first release
|
--
|
--
|
-- known bugs/todo:
|
-- known bugs/todo:
|
-- Add CHK INSTRUCTION
|
-- Add CHK INSTRUCTION
|
-- Add MOVEP INSTRUCTION
|
|
-- full decode ILLEGAL INSTRUCTIONS
|
-- full decode ILLEGAL INSTRUCTIONS
|
-- Add FDC Output
|
-- Add FDC Output
|
-- add odd Address test
|
-- add odd Address test
|
-- add TRACE
|
-- add TRACE
|
-- Movem with regmask==x0000
|
-- Movem with regmask==x0000
|
| Line 234... |
Line 238... |
signal one_bit_in : std_logic;
|
signal one_bit_in : std_logic;
|
signal one_bit_out : std_logic;
|
signal one_bit_out : std_logic;
|
signal set_get_bitnumber : std_logic;
|
signal set_get_bitnumber : std_logic;
|
signal get_bitnumber : std_logic;
|
signal get_bitnumber : std_logic;
|
signal mem_byte : std_logic;
|
signal mem_byte : std_logic;
|
|
signal wait_mem_byte : std_logic;
|
|
signal movepl : std_logic;
|
|
signal movepw : std_logic;
|
|
signal set_movepl : std_logic;
|
|
signal set_movepw : std_logic;
|
signal set_direct_data: std_logic;
|
signal set_direct_data: std_logic;
|
signal use_direct_data: std_logic;
|
signal use_direct_data: std_logic;
|
signal direct_data : std_logic;
|
signal direct_data : std_logic;
|
signal set_get_extendedOPC : std_logic;
|
signal set_get_extendedOPC : std_logic;
|
signal get_extendedOPC: std_logic;
|
signal get_extendedOPC: std_logic;
|
| Line 281... |
Line 290... |
signal trap_1010 : std_logic;
|
signal trap_1010 : std_logic;
|
signal trap_1111 : std_logic;
|
signal trap_1111 : std_logic;
|
signal trap_trap : std_logic;
|
signal trap_trap : std_logic;
|
signal trap_trapv : std_logic;
|
signal trap_trapv : std_logic;
|
signal trap_interrupt : std_logic;
|
signal trap_interrupt : std_logic;
|
signal trap : std_logic;
|
signal trapmake : std_logic;
|
signal trapd : std_logic;
|
signal trapd : std_logic;
|
-- signal trap_PC : std_logic_vector(31 downto 0);
|
-- signal trap_PC : std_logic_vector(31 downto 0);
|
signal trap_SR : std_logic_vector(15 downto 0);
|
signal trap_SR : std_logic_vector(15 downto 0);
|
|
|
signal set_directSR : std_logic;
|
signal set_directSR : std_logic;
|
| Line 305... |
Line 314... |
signal no_Flags : std_logic;
|
signal no_Flags : std_logic;
|
signal IPL_nr : std_logic_vector(2 downto 0);
|
signal IPL_nr : std_logic_vector(2 downto 0);
|
signal rIPL_nr : std_logic_vector(2 downto 0);
|
signal rIPL_nr : std_logic_vector(2 downto 0);
|
signal interrupt : std_logic;
|
signal interrupt : std_logic;
|
signal SVmode : std_logic;
|
signal SVmode : std_logic;
|
signal check_movep : std_logic;
|
signal trap_chk : std_logic;
|
signal check_chk : std_logic;
|
|
signal test_delay : std_logic_vector(2 downto 0);
|
signal test_delay : std_logic_vector(2 downto 0);
|
signal set_PCmarker : std_logic;
|
signal set_PCmarker : std_logic;
|
signal PCmarker : std_logic;
|
signal PCmarker : std_logic;
|
signal set_Z_error : std_logic;
|
signal set_Z_error : std_logic;
|
signal Z_error : std_logic;
|
signal Z_error : std_logic;
|
| Line 381... |
Line 389... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- MEM_IO
|
-- MEM_IO
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, trap_illegal, z_error, trap_trapv, trap_priv, trap_1010, trap_1111, trap_trap,
|
--PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, trap_illegal, z_error, trap_trapv, trap_priv, trap_1010, trap_1111, trap_trap,
|
memaddr, memaddr_a, set_mem_addsub, movem_presub, movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
|
-- memaddr, memaddr_a, set_mem_addsub, movem_presub, movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
|
trap_vector, interrupt, set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
|
-- trap_vector, interrupt, set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
|
|
-- data_write_tmp, addsub_q, set_vectoraddr)
|
|
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
|
|
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
|
|
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
|
data_write_tmp, addsub_q, set_vectoraddr)
|
data_write_tmp, addsub_q, set_vectoraddr)
|
BEGIN
|
BEGIN
|
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
|
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
|
|
|
-- IF rising_edge(clk) THEN
|
IF rising_edge(clk) THEN
|
-- IF clkena='1' THEN
|
IF clkena='1' THEN
|
-- trap_vector <= "000000000000000000000000011"&rIPL_nr&"00";
|
trap_vector(31 downto 8) <= (others => '0');
|
trap_vector <= (others => '0');
|
|
-- IF trap_addr_fault='1' THEN
|
-- IF trap_addr_fault='1' THEN
|
-- trap_vector(7 downto 0) <= X"08";
|
-- trap_vector(7 downto 0) <= X"08";
|
-- END IF;
|
-- END IF;
|
-- IF trap_addr_error='1' THEN
|
-- IF trap_addr_error='1' THEN
|
-- trap_vector(7 downto 0) <= X"0C";
|
-- trap_vector(7 downto 0) <= X"0C";
|
-- END IF;
|
-- END IF;
|
IF trap_illegal='1' THEN
|
IF trap_illegal='1' THEN
|
trap_vector(7 downto 0) <= X"10";
|
trap_vector(7 downto 0) <= X"10";
|
-- END IF;
|
END IF;
|
ELSIF z_error='1' THEN
|
IF z_error='1' THEN
|
trap_vector(7 downto 0) <= X"14";
|
trap_vector(7 downto 0) <= X"14";
|
-- END IF;
|
END IF;
|
-- IF trap_chk='1' THEN
|
-- IF trap_chk='1' THEN
|
-- trap_vector(7 downto 0) <= X"18";
|
-- trap_vector(7 downto 0) <= X"18";
|
-- END IF;
|
-- END IF;
|
ELSIF trap_trapv='1' THEN
|
IF trap_trapv='1' THEN
|
trap_vector(7 downto 0) <= X"1C";
|
trap_vector(7 downto 0) <= X"1C";
|
-- END IF;
|
END IF;
|
ELSIF trap_priv='1' THEN
|
IF trap_priv='1' THEN
|
trap_vector(7 downto 0) <= X"20";
|
trap_vector(7 downto 0) <= X"20";
|
-- END IF;
|
END IF;
|
-- IF trap_trace='1' THEN
|
-- IF trap_trace='1' THEN
|
-- trap_vector(7 downto 0) <= X"24";
|
-- trap_vector(7 downto 0) <= X"24";
|
-- END IF;
|
-- END IF;
|
ELSIF trap_1010='1' THEN
|
IF trap_1010='1' THEN
|
trap_vector(7 downto 0) <= X"28";
|
trap_vector(7 downto 0) <= X"28";
|
-- END IF;
|
END IF;
|
ELSIF trap_1111='1' THEN
|
IF trap_1111='1' THEN
|
trap_vector(7 downto 0) <= X"2C";
|
trap_vector(7 downto 0) <= X"2C";
|
-- END IF;
|
END IF;
|
ELSIF trap_trap='1' THEN
|
IF trap_trap='1' THEN
|
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
|
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
|
-- ELSIF trap_interrupt='1' THEN
|
END IF;
|
ELSE
|
IF interrupt='1' THEN
|
trap_vector(7 downto 2) <= "011"&rIPL_nr;
|
trap_vector(7 downto 2) <= "011"&rIPL_nr;
|
-- END IF;
|
END IF;
|
-- END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
memaddr_a(3 downto 0) <= "0000";
|
memaddr_a(3 downto 0) <= "0000";
|
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
|
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
|
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
|
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
|
| Line 611... |
Line 622... |
mem_byte <= '0';
|
mem_byte <= '0';
|
rot_cnt <="000001";
|
rot_cnt <="000001";
|
get_extendedOPC <= '0';
|
get_extendedOPC <= '0';
|
get_bitnumber <= '0';
|
get_bitnumber <= '0';
|
get_movem_mask <= '0';
|
get_movem_mask <= '0';
|
|
movepl <= '0';
|
|
movepw <= '0';
|
test_delay <= "000";
|
test_delay <= "000";
|
PCmarker <= '0';
|
PCmarker <= '0';
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena_in='1' THEN
|
IF clkena_in='1' THEN
|
get_extendedOPC <= set_get_extendedOPC;
|
get_extendedOPC <= set_get_extendedOPC;
|
| Line 643... |
Line 656... |
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
|
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
|
state <= "01"; --decode cycle, execute cycle
|
state <= "01"; --decode cycle, execute cycle
|
ELSE
|
ELSE
|
state <= setstate_mux;
|
state <= setstate_mux;
|
END IF;
|
END IF;
|
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' THEN
|
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
|
mem_byte <= '1';
|
mem_byte <= '1';
|
ELSE
|
ELSE
|
mem_byte <= '0';
|
mem_byte <= '0';
|
END IF;
|
END IF;
|
|
|
| Line 677... |
Line 690... |
decodeOPC <= fetchOPC;
|
decodeOPC <= fetchOPC;
|
directPC <= set_directPC;
|
directPC <= set_directPC;
|
directSR <= set_directSR;
|
directSR <= set_directSR;
|
exec_MULU <= set_exec_MULU;
|
exec_MULU <= set_exec_MULU;
|
exec_DIVU <= set_exec_DIVU;
|
exec_DIVU <= set_exec_DIVU;
|
|
movepl <= '0';
|
|
movepw <= '0';
|
|
|
stop <= set_stop OR (stop AND NOT interrupt);
|
stop <= set_stop OR (stop AND NOT interrupt);
|
IF set_PCmarker='1' THEN
|
IF set_PCmarker='1' THEN
|
PCmarker <= '1';
|
PCmarker <= '1';
|
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
|
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
|
| Line 689... |
Line 704... |
IF (decodeOPC OR execOPC)='1' THEN
|
IF (decodeOPC OR execOPC)='1' THEN
|
rot_cnt <= set_rot_cnt;
|
rot_cnt <= set_rot_cnt;
|
END IF;
|
END IF;
|
IF microstep='0' AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
IF microstep='0' AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
nextpass <= '0';
|
nextpass <= '0';
|
-- IF stop='0' THEN
|
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
endOPC <= '1';
|
endOPC <= '1';
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
interrupt <= '1';
|
interrupt <= '1';
|
trap_interrupt <= '1';
|
|
rIPL_nr <= IPL_nr;
|
rIPL_nr <= IPL_nr;
|
ELSE
|
ELSE
|
IF stop='0' THEN
|
IF stop='0' THEN
|
fetchOPC <= '1';
|
fetchOPC <= '1';
|
END IF;
|
END IF;
|
| Line 723... |
Line 736... |
exec_ABCD <= set_exec_ABCD;
|
exec_ABCD <= set_exec_ABCD;
|
exec_SBCD <= set_exec_SBCD;
|
exec_SBCD <= set_exec_SBCD;
|
exec_Scc <= set_exec_Scc;
|
exec_Scc <= set_exec_Scc;
|
exec_CPMAW <= set_exec_CPMAW;
|
exec_CPMAW <= set_exec_CPMAW;
|
END IF;
|
END IF;
|
-- END IF;
|
|
ELSE
|
ELSE
|
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
|
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
|
nextpass <= '1';
|
nextpass <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
opcode(15 downto 12) <= X"7"; --moveq
|
opcode(15 downto 12) <= X"7"; --moveq
|
opcode(8 downto 6) <= "010"; --long
|
opcode(8 downto 6) <= "010"; --long
|
-- trap_PC <= TG68_PC;
|
-- trap_PC <= TG68_PC;
|
|
trap_interrupt <= '1';
|
END IF;
|
END IF;
|
IF fetchOPC='1' THEN
|
IF fetchOPC='1' THEN
|
trap_interrupt <= '0';
|
trap_interrupt <= '0';
|
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
|
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
|
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
|
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
|
| Line 750... |
Line 763... |
getbrief <= '0';
|
getbrief <= '0';
|
-- trap_PC <= TG68_PC;
|
-- trap_PC <= TG68_PC;
|
ELSE
|
ELSE
|
test_delay <= test_delay(1 downto 0)&'0';
|
test_delay <= test_delay(1 downto 0)&'0';
|
getbrief <= setgetbrief;
|
getbrief <= setgetbrief;
|
|
movepl <= set_movepl;
|
|
movepw <= set_movepw;
|
END IF;
|
END IF;
|
IF decodeOPC='1' OR interrupt='1' THEN
|
IF decodeOPC='1' OR interrupt='1' THEN
|
trap_SR <= Flags;
|
trap_SR <= Flags;
|
END IF;
|
END IF;
|
|
|
| Line 813... |
Line 828... |
data_write_tmp <= TG68_PC;
|
data_write_tmp <= TG68_PC;
|
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
|
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
|
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
|
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
|
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
|
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
|
data_write_tmp <= data_read;
|
data_write_tmp <= data_read;
|
ELSIF movem_busy='1' AND datatype="10" AND movem_presub='1' THEN
|
IF movepl='1' THEN
|
|
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
|
|
END IF;
|
|
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
|
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
|
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
|
ELSIF (NOT trap AND decodeOPC)='1' OR movem_busy='1'THEN
|
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
|
data_write_tmp <= OP2out;
|
data_write_tmp <= OP2out;
|
ELSIF writeSR='1'THEN
|
ELSIF writeSR='1'THEN
|
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
|
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 827... |
Line 845... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- set dest regaddr
|
-- set dest regaddr
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trap, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
|
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
|
BEGIN
|
BEGIN
|
rf_dest_addr <= rf_dest_addr_tmp;
|
rf_dest_addr <= rf_dest_addr_tmp;
|
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
|
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
|
rf_dest_addr(4) <= Flags(13) OR trap;
|
rf_dest_addr(4) <= Flags(13) OR trapmake;
|
END IF;
|
END IF;
|
IF movem_addr='1' THEN
|
IF movem_addr='1' THEN
|
IF movem_presub='1' THEN
|
IF movem_presub='1' THEN
|
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
ELSE
|
ELSE
|
| Line 921... |
Line 939... |
OP2out(3) <='1';
|
OP2out(3) <='1';
|
ELSE
|
ELSE
|
OP2out(3) <='0';
|
OP2out(3) <='0';
|
END IF;
|
END IF;
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
ELSIF datatype="10" THEN
|
ELSIF datatype="10" OR movepl='1' THEN
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 1103... |
Line 1121... |
IF opcode(8)='0' THEN
|
IF opcode(8)='0' THEN
|
Flags(3 downto 0) <= "1000";
|
Flags(3 downto 0) <= "1000";
|
ELSE
|
ELSE
|
Flags(3 downto 0) <= "0100";
|
Flags(3 downto 0) <= "0100";
|
END IF;
|
END IF;
|
ELSIF no_Flags='0' AND trap='0' THEN
|
ELSIF no_Flags='0' AND trapmake='0' THEN
|
IF exec_ADD='1' THEN
|
IF exec_ADD='1' THEN
|
Flags(4) <= set_flags(0);
|
Flags(4) <= set_flags(0);
|
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
|
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
|
Flags(4) <= rot_XC;
|
Flags(4) <= rot_XC;
|
END IF;
|
END IF;
|
| Line 1139... |
Line 1157... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- execute opcode
|
-- execute opcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trap, trapd, interrupt, trap_interrupt,
|
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
|
Z_error, microaddr, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
|
Z_error, microaddr, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
|
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec)
|
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec)
|
BEGIN
|
BEGIN
|
TG68_PC_br8 <= '0';
|
TG68_PC_br8 <= '0';
|
TG68_PC_brw <= '0';
|
TG68_PC_brw <= '0';
|
| Line 1222... |
Line 1240... |
trap_priv <='0';
|
trap_priv <='0';
|
trap_1010 <='0';
|
trap_1010 <='0';
|
trap_1111 <='0';
|
trap_1111 <='0';
|
trap_trap <='0';
|
trap_trap <='0';
|
trap_trapv <= '0';
|
trap_trapv <= '0';
|
trap <='0';
|
trapmake <='0';
|
set_vectoraddr <='0';
|
set_vectoraddr <='0';
|
writeSR <= '0';
|
writeSR <= '0';
|
set_directSR <= '0';
|
set_directSR <= '0';
|
set_stop <= '0';
|
set_stop <= '0';
|
from_SR <= '0';
|
from_SR <= '0';
|
| Line 1238... |
Line 1256... |
illegal_byteaddr <= '0';
|
illegal_byteaddr <= '0';
|
no_Flags <= '0';
|
no_Flags <= '0';
|
set_PCmarker <= '0';
|
set_PCmarker <= '0';
|
use_SP <= '0';
|
use_SP <= '0';
|
set_Z_error <= '0';
|
set_Z_error <= '0';
|
|
wait_mem_byte <= '0';
|
|
set_movepl <= '0';
|
|
set_movepw <= '0';
|
|
|
check_movep <= '0';
|
trap_chk <= '0';
|
check_chk <= '0';
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--Sourcepass
|
--Sourcepass
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
IF ea_only='0' AND get_ea_now='1' THEN
|
IF ea_only='0' AND get_ea_now='1' THEN
|
| Line 1344... |
Line 1364... |
|
|
|
|
CASE opcode(15 downto 12) IS
|
CASE opcode(15 downto 12) IS
|
-- 0000 ----------------------------------------------------------------------------
|
-- 0000 ----------------------------------------------------------------------------
|
WHEN "0000" =>
|
WHEN "0000" =>
|
--hier muss noch MOVEP rein
|
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
trap_illegal <= '1';
|
datatype <= "00"; --Byte
|
trap <= '1';
|
use_SP <= '1';
|
|
no_Flags <='1';
|
|
IF opcode(7)='0' THEN
|
|
set_exec_move <= '1';
|
|
set_movepl <= '1';
|
|
END IF;
|
|
IF decodeOPC='1' THEN
|
|
IF opcode(7)='0' THEN
|
|
set_direct_data <= '1';
|
|
END IF;
|
|
microstep <='1';
|
|
micronext <="01010110";
|
|
setgetbrief <='1';
|
|
set_mem_regA <= '1';
|
|
END IF;
|
|
IF opcode(7)='0' AND endOPC='1' THEN
|
|
IF opcode(6)='1' THEN
|
|
datatype <= "10"; --Long
|
|
ELSE
|
|
datatype <= "01"; --Word
|
|
END IF;
|
|
dest_hbits <='1';
|
|
regwrena <= '1';
|
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
|
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
|
IF execOPC='1' AND get_extendedOPC='0' THEN
|
IF execOPC='1' AND get_extendedOPC='0' THEN
|
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
|
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
| Line 1392... |
Line 1434... |
IF opcode(11 downto 8)="1010" THEN --EORI
|
IF opcode(11 downto 8)="1010" THEN --EORI
|
set_exec_EOR <= '1';
|
set_exec_EOR <= '1';
|
END IF;
|
END IF;
|
IF opcode(11 downto 8)="1100" THEN --CMPI
|
IF opcode(11 downto 8)="1100" THEN --CMPI
|
set_exec_CMP <= '1';
|
set_exec_CMP <= '1';
|
ELSIF trap='0' THEN
|
ELSIF trapmake='0' THEN
|
write_back <= '1';
|
write_back <= '1';
|
END IF;
|
END IF;
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
|
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
|
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
|
IF SVmode='0' AND opcode(6)='1' THEN --SR
|
IF SVmode='0' AND opcode(6)='1' THEN --SR
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
from_SR <= '1';
|
from_SR <= '1';
|
to_SR <= '1';
|
to_SR <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setnextpass <= '1';
|
setnextpass <= '1';
|
| Line 1555... |
Line 1597... |
dest_hbits <= '1';
|
dest_hbits <= '1';
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --chk
|
ELSE --chk
|
trap_illegal <= '1';
|
IF opcode(7)='1' THEN
|
trap <= '1';
|
set_exec_ADD <= '1';
|
check_chk <= '1';
|
IF decodeOPC='1' THEN
|
|
ea_build <= '1';
|
|
END IF;
|
|
datatype <= "01"; --Word
|
|
IF execOPC='1' THEN
|
|
setaddsub <= '0';
|
|
--first alternative
|
|
ea_data_OP1 <= '1';
|
|
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
|
|
-- trap_chk <= '1'; --first I must change the Trap System
|
|
-- trapmake <= '1';
|
|
END IF;
|
|
--second alternative
|
|
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
|
|
-- -- trap_chk <= '1'; --first I must change the Trap System
|
|
-- -- trapmake <= '1';
|
|
-- END IF;
|
|
-- dest_hbits <= '1';
|
|
-- source_lowbits <='1';
|
|
END IF;
|
|
ELSE
|
|
trap_illegal <= '1'; -- chk long for 68020
|
|
trapmake <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
CASE opcode(11 downto 9) IS
|
CASE opcode(11 downto 9) IS
|
WHEN "000"=>
|
WHEN "000"=>
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
| Line 1593... |
Line 1658... |
END IF;
|
END IF;
|
END IF;
|
END IF;
|
WHEN "001"=>
|
WHEN "001"=>
|
IF opcode(7downto 6)="11" THEN --move from CCR 68010
|
IF opcode(7downto 6)="11" THEN --move from CCR 68010
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
ELSE --clr
|
ELSE --clr
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
write_back <='1';
|
write_back <='1';
|
| Line 1644... |
Line 1709... |
source_lowbits <= '1';
|
source_lowbits <= '1';
|
to_SR <= '1';
|
to_SR <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --not
|
ELSE --not
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
| Line 1733... |
Line 1798... |
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
IF opcode(10)='1' THEN --MUL, DIV 68020
|
IF opcode(10)='1' THEN --MUL, DIV 68020
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
ELSE --pea, swap
|
ELSE --pea, swap
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
datatype <= "10";
|
datatype <= "10";
|
IF opcode(5 downto 3)="000" THEN --swap
|
IF opcode(5 downto 3)="000" THEN --swap
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
| Line 1830... |
Line 1895... |
ELSE --
|
ELSE --
|
CASE opcode(6 downto 0) IS
|
CASE opcode(6 downto 0) IS
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
trap_trap <='1';
|
trap_trap <='1';
|
trap <= '1';
|
trapmake <= '1';
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
datatype <= "10";
|
datatype <= "10";
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
micronext <="01000000";
|
micronext <="01000000";
|
microstep <='1';
|
microstep <='1';
|
| Line 1877... |
Line 1942... |
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
IF SVmode='1' THEN
|
IF SVmode='1' THEN
|
no_Flags <= '1';
|
no_Flags <= '1';
|
from_USP <= '1';
|
from_USP <= '1';
|
| Line 1890... |
Line 1955... |
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110000" => --reset
|
WHEN "1110000" => --reset
|
IF SVmode='0' THEN
|
IF SVmode='0' THEN
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110001" => --nop
|
WHEN "1110001" => --nop
|
|
|
WHEN "1110010" => --stop
|
WHEN "1110010" => --stop
|
IF SVmode='0' THEN
|
IF SVmode='0' THEN
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
ELSE
|
ELSE
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
setnextpass <= '1';
|
setnextpass <= '1';
|
set_directSR <= '1';
|
set_directSR <= '1';
|
set_stop <= '1';
|
set_stop <= '1';
|
| Line 1927... |
Line 1992... |
microstep <='1';
|
microstep <='1';
|
micronext <= "01001000";
|
micronext <= "01001000";
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "1110101" => --rts
|
WHEN "1110101" => --rts
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
datatype <= "10";
|
datatype <= "10";
|
| Line 1944... |
Line 2009... |
END IF;
|
END IF;
|
|
|
WHEN "1110110" => --trapv
|
WHEN "1110110" => --trapv
|
IF Flags(1)='1' THEN
|
IF Flags(1)='1' THEN
|
trap_trapv <= '1';
|
trap_trapv <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
|
|
| Line 2053... |
Line 2118... |
set_exec_MOVE <= '1';
|
set_exec_MOVE <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
|
|
-- 1000 ----------------------------------------------------------------------------
|
-- 1000 ----------------------------------------------------------------------------
|
WHEN "1000" => --or
|
WHEN "1000" => --or
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
| Line 2108... |
Line 2173... |
Regwrena <= '1';
|
Regwrena <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
ELSE --pack, unpack
|
ELSE --pack, unpack
|
trap_illegal <= '1';
|
trap_illegal <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
ELSE --or
|
ELSE --or
|
set_exec_OR <= '1';
|
set_exec_OR <= '1';
|
IF opcode(8)='1' THEN
|
IF opcode(8)='1' THEN
|
write_back <= '1';
|
write_back <= '1';
|
| Line 2199... |
Line 2264... |
END IF;
|
END IF;
|
|
|
-- 1010 ----------------------------------------------------------------------------
|
-- 1010 ----------------------------------------------------------------------------
|
WHEN "1010" => --Trap 1010
|
WHEN "1010" => --Trap 1010
|
trap_1010 <= '1';
|
trap_1010 <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
-- 1011 ----------------------------------------------------------------------------
|
-- 1011 ----------------------------------------------------------------------------
|
WHEN "1011" => --eor, cmp
|
WHEN "1011" => --eor, cmp
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
| Line 2387... |
Line 2452... |
END IF;
|
END IF;
|
|
|
-- ----------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
trap_1111 <= '1';
|
trap_1111 <= '1';
|
trap <= '1';
|
trapmake <= '1';
|
|
|
END CASE;
|
END CASE;
|
|
|
-- END PROCESS;
|
-- END PROCESS;
|
|
|
| Line 2399... |
Line 2464... |
-- execute microcode
|
-- execute microcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--PROCESS (microaddr)
|
--PROCESS (microaddr)
|
-- BEGIN
|
-- BEGIN
|
IF Z_error='1' THEN -- divu by zero
|
IF Z_error='1' THEN -- divu by zero
|
trap <= '1'; --wichtig für USP
|
trapmake <= '1'; --wichtig für USP
|
IF trapd='0' THEN
|
IF trapd='0' THEN
|
writePC <= '1';
|
writePC <= '1';
|
microset <= '1';
|
microset <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF trap='1' AND trapd='0' THEN
|
IF trapmake='1' AND trapd='0' THEN
|
microstep <= '1';
|
microstep <= '1';
|
micronext <= "01010000";
|
micronext <= "01010000";
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
| Line 2429... |
Line 2494... |
IF reset='0' THEN
|
IF reset='0' THEN
|
microaddr <= "01100000"; --init
|
microaddr <= "01100000"; --init
|
prefix <= '1';
|
prefix <= '1';
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
trapd <= trap;
|
trapd <= trapmake;
|
prefix <= (prefix AND ea_build) OR (microstep AND NOT fetchOPC);
|
prefix <= (prefix AND ea_build) OR (microstep AND NOT fetchOPC);
|
IF prefix='1' AND ea_build='0' AND microset='0' THEN
|
IF prefix='1' AND ea_build='0' AND microset='0' THEN
|
microaddr <= microaddr + micronext;
|
microaddr <= microaddr + micronext;
|
ELSE
|
ELSE
|
microaddr <= micronext;
|
microaddr <= micronext;
|
| Line 2618... |
Line 2683... |
-- longreaddirect <= '1';
|
-- longreaddirect <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
WHEN "01010010" => -- TRAP
|
WHEN "01010010" => -- TRAP
|
datatype <= "10";
|
datatype <= "10";
|
|
|
|
WHEN "01010110" => -- MOVEP d(An)
|
|
microstep <='1';
|
|
setstate <= "01";
|
|
IF opcode(6)='1' THEN
|
|
set_movepl <= '1';
|
|
END IF;
|
|
WHEN "01010111" =>
|
|
microstep <='1';
|
|
setdisp <= '1';
|
|
IF opcode(7)='0' THEN
|
|
setstate <= "10";
|
|
ELSE
|
|
setstate <= "11";
|
|
wait_mem_byte <= '1';
|
|
END IF;
|
|
WHEN "01011000" =>
|
|
IF opcode(6)='1' THEN
|
|
microstep <='1';
|
|
set_movepw <= '1';
|
|
END IF;
|
|
IF opcode(7)='0' THEN
|
|
setstate <= "10";
|
|
ELSE
|
|
setstate <= "11";
|
|
END IF;
|
|
WHEN "01011001" =>
|
|
microstep <='1';
|
|
|
|
IF opcode(7)='0' THEN
|
|
setstate <= "10";
|
|
ELSE
|
|
wait_mem_byte <= '1';
|
|
setstate <= "11";
|
|
END IF;
|
|
WHEN "01011010" =>
|
|
IF opcode(7)='0' THEN
|
|
setstate <= "10";
|
|
ELSE
|
|
setstate <= "11";
|
|
END IF;
|
|
|
|
|
|
|
|
|
|
|
WHEN "01100000" => -- init SP
|
WHEN "01100000" => -- init SP
|
microstep <='1';
|
microstep <='1';
|
