| Line 20... |
Line 20... |
-- --
|
-- --
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--
|
--
|
--
|
--
|
|
-- Revision 1.04 2007/12/29
|
|
-- size improvement
|
|
-- change signal "microaddr" to one hot state machine
|
|
--
|
-- Revision 1.03 2007/12/21
|
-- Revision 1.03 2007/12/21
|
-- Thanks to Andreas Ehliar
|
-- Thanks to Andreas Ehliar
|
-- Split regfile to use blockram for registers
|
-- Split regfile to use blockram for registers
|
-- insert "WHEN OTHERS => null;" on END CASE;
|
-- insert "WHEN OTHERS => null;" on END CASE;
|
--
|
--
|
| Line 91... |
Line 95... |
signal nextpass : std_logic;
|
signal nextpass : std_logic;
|
signal setnextpass : std_logic;
|
signal setnextpass : std_logic;
|
signal setdispbyte : std_logic;
|
signal setdispbyte : std_logic;
|
signal setdisp : std_logic;
|
signal setdisp : std_logic;
|
signal setdispbrief : std_logic;
|
signal setdispbrief : std_logic;
|
signal prefix : std_logic;
|
|
signal regdirectsource : std_logic;
|
signal regdirectsource : std_logic;
|
signal endOPC : std_logic;
|
signal endOPC : std_logic;
|
signal postadd : std_logic;
|
signal postadd : std_logic;
|
signal presub : std_logic;
|
signal presub : std_logic;
|
signal addsub_a : std_logic_vector(31 downto 0);
|
signal addsub_a : std_logic_vector(31 downto 0);
|
| Line 110... |
Line 113... |
signal addsub_ofl : std_logic_vector(2 downto 0);
|
signal addsub_ofl : std_logic_vector(2 downto 0);
|
signal flag_z : std_logic_vector(2 downto 0);
|
signal flag_z : std_logic_vector(2 downto 0);
|
|
|
signal last_data_read : std_logic_vector(15 downto 0);
|
signal last_data_read : std_logic_vector(15 downto 0);
|
signal data_read : std_logic_vector(31 downto 0);
|
signal data_read : std_logic_vector(31 downto 0);
|
signal microaddr : std_logic_vector(7 downto 0);
|
|
signal micronext : std_logic_vector(7 downto 0);
|
|
signal microstep : std_logic;
|
|
signal microset : std_logic;
|
|
|
|
signal registerin : std_logic_vector(31 downto 0);
|
signal registerin : std_logic_vector(31 downto 0);
|
signal reg_QA : std_logic_vector(31 downto 0);
|
signal reg_QA : std_logic_vector(31 downto 0);
|
signal reg_QB : std_logic_vector(31 downto 0);
|
signal reg_QB : std_logic_vector(31 downto 0);
|
signal Hwrena,Lwrena : std_logic;
|
signal Hwrena,Lwrena : std_logic;
|
| Line 329... |
Line 328... |
signal set_PCmarker : std_logic;
|
signal set_PCmarker : std_logic;
|
signal PCmarker : std_logic;
|
signal PCmarker : std_logic;
|
signal set_Z_error : std_logic;
|
signal set_Z_error : std_logic;
|
signal Z_error : std_logic;
|
signal Z_error : std_logic;
|
|
|
|
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
|
|
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
|
|
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
|
|
movep1, movep2, movep3, movep4, movep5, init1, init2,
|
|
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
|
|
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
|
|
signal micro_state : micro_states;
|
|
signal next_micro_state : micro_states;
|
|
|
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
|
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
|
signal regfile_low : regfile_t;
|
signal regfile_low : regfile_t;
|
signal regfile_high : regfile_t;
|
signal regfile_high : regfile_t;
|
signal RWindex_A : integer range 0 to 16;
|
signal RWindex_A : integer range 0 to 16;
|
signal RWindex_B : integer range 0 to 16;
|
signal RWindex_B : integer range 0 to 16;
|
|
|
|
|
BEGIN
|
BEGIN
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Registerfile
|
-- Registerfile
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 706... |
Line 715... |
PCmarker <= '0';
|
PCmarker <= '0';
|
END IF;
|
END IF;
|
IF (decodeOPC OR execOPC)='1' THEN
|
IF (decodeOPC OR execOPC)='1' THEN
|
rot_cnt <= set_rot_cnt;
|
rot_cnt <= set_rot_cnt;
|
END IF;
|
END IF;
|
IF microstep='0' AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
nextpass <= '0';
|
nextpass <= '0';
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
endOPC <= '1';
|
endOPC <= '1';
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
interrupt <= '1';
|
interrupt <= '1';
|
| Line 1162... |
Line 1171... |
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- execute opcode
|
-- execute opcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
|
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
|
Z_error, microaddr, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
|
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
|
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out)
|
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
|
BEGIN
|
BEGIN
|
TG68_PC_br8 <= '0';
|
TG68_PC_br8 <= '0';
|
TG68_PC_brw <= '0';
|
TG68_PC_brw <= '0';
|
TG68_PC_nop <= '0';
|
TG68_PC_nop <= '0';
|
setstate <= "00";
|
setstate <= "00";
|
Regwrena <= '0';
|
Regwrena <= '0';
|
microstep <= '0';
|
|
microset <= '0';
|
|
postadd <= '0';
|
postadd <= '0';
|
presub <= '0';
|
presub <= '0';
|
movem_presub <= '0';
|
movem_presub <= '0';
|
setaddsub <= '1';
|
setaddsub <= '1';
|
micronext <= "00000001";
|
|
setaddrlong <= '0';
|
setaddrlong <= '0';
|
setnextpass <= '0';
|
setnextpass <= '0';
|
regdirectsource <= '0';
|
regdirectsource <= '0';
|
setdisp <= '0';
|
setdisp <= '0';
|
setdispbyte <= '0';
|
setdispbyte <= '0';
|
| Line 1266... |
Line 1272... |
wait_mem_byte <= '0';
|
wait_mem_byte <= '0';
|
set_movepl <= '0';
|
set_movepl <= '0';
|
set_movepw <= '0';
|
set_movepw <= '0';
|
|
|
trap_chk <= '0';
|
trap_chk <= '0';
|
|
next_micro_state <= idle;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--Sourcepass
|
--Sourcepass
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
IF ea_only='0' AND get_ea_now='1' THEN
|
IF ea_only='0' AND get_ea_now='1' THEN
|
| Line 1300... |
Line 1307... |
END IF;
|
END IF;
|
IF opcode(4 downto 3)/="10" THEN
|
IF opcode(4 downto 3)/="10" THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
WHEN "101" => --(d16,An)
|
WHEN "101" => --(d16,An)
|
microstep <='1';
|
next_micro_state <= ld_dAn1;
|
micronext <="00000110";
|
|
setgetbrief <='1';
|
setgetbrief <='1';
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
WHEN "110" => --(d8,An,Xn)
|
WHEN "110" => --(d8,An,Xn)
|
microstep <='1';
|
next_micro_state <= ld_AnXn1;
|
micronext <="00001000";
|
|
setgetbrief <='1';
|
setgetbrief <='1';
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
WHEN "111" =>
|
WHEN "111" =>
|
CASE opcode(2 downto 0) IS
|
CASE opcode(2 downto 0) IS
|
WHEN "000" => --(xxxx).w
|
WHEN "000" => --(xxxx).w
|
micronext <="00000010";
|
next_micro_state <= ld_nn;
|
microstep <='1';
|
|
WHEN "001" => --(xxxx).l
|
WHEN "001" => --(xxxx).l
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
micronext <="00000010";
|
next_micro_state <= ld_nn;
|
microstep <='1';
|
|
WHEN "010" => --(d16,PC)
|
WHEN "010" => --(d16,PC)
|
microstep <='1';
|
next_micro_state <= ld_dAn1;
|
micronext <="00000110";
|
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
set_PCmarker <= '1';
|
set_PCmarker <= '1';
|
WHEN "011" => --(d8,PC,Xn)
|
WHEN "011" => --(d8,PC,Xn)
|
microstep <='1';
|
next_micro_state <= ld_AnXn1;
|
micronext <="00001000";
|
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
set_PCmarker <= '1';
|
set_PCmarker <= '1';
|
WHEN "100" => --#data
|
WHEN "100" => --#data
|
setnextpass <= '1';
|
setnextpass <= '1';
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
| Line 1381... |
Line 1382... |
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
END IF;
|
END IF;
|
microstep <='1';
|
next_micro_state <= movep1;
|
micronext <="01010110";
|
|
setgetbrief <='1';
|
setgetbrief <='1';
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
END IF;
|
END IF;
|
IF opcode(7)='0' AND endOPC='1' THEN
|
IF opcode(7)='0' AND endOPC='1' THEN
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
| Line 1462... |
Line 1462... |
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
|
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
|
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
|
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
|
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
|
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
|
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
|
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
|
|
|
microstep <='1';
|
next_micro_state <= andi;
|
micronext <="00101000";
|
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
IF datatype="10" THEN
|
IF datatype="10" THEN
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 1523... |
Line 1522... |
|
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
|
|
IF prefix='0' AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
|
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
|
CASE opcode(8 downto 6) IS --destination
|
CASE opcode(8 downto 6) IS --destination
|
-- WHEN "000" => --Dn
|
-- WHEN "000" => --Dn
|
-- WHEN "001" => --An
|
-- WHEN "001" => --An
|
WHEN "010"|"011"|"100" => --destination -(an)+
|
WHEN "010"|"011"|"100" => --destination -(an)+
|
IF opcode(7)='1' THEN
|
IF opcode(7)='1' THEN
|
| Line 1549... |
Line 1548... |
END IF;
|
END IF;
|
IF opcode(7 downto 6)/="10" THEN
|
IF opcode(7 downto 6)/="10" THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
setstate <= "11";
|
setstate <= "11";
|
microstep <='1'; --nop
|
next_micro_state <= nop;
|
WHEN "101" => --(d16,An)
|
WHEN "101" => --(d16,An)
|
microstep <='1';
|
next_micro_state <= st_dAn1;
|
micronext <="00001011";
|
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
WHEN "110" => --(d8,An,Xn)
|
WHEN "110" => --(d8,An,Xn)
|
microstep <='1';
|
next_micro_state <= st_AnXn1;
|
micronext <="00001110";
|
|
set_mem_regA <= '1';
|
set_mem_regA <= '1';
|
setgetbrief <= '1';
|
setgetbrief <= '1';
|
WHEN "111" =>
|
WHEN "111" =>
|
CASE opcode(11 downto 9) IS
|
CASE opcode(11 downto 9) IS
|
WHEN "000" => --(xxxx).w
|
WHEN "000" => --(xxxx).w
|
microstep <='1';
|
next_micro_state <= st_nn;
|
micronext <="00000011";
|
|
WHEN "001" => --(xxxx).l
|
WHEN "001" => --(xxxx).l
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
microstep <='1';
|
next_micro_state <= st_nn;
|
micronext <="00000011";
|
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
| Line 1758... |
Line 1753... |
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
setstate <= "01";
|
setstate <= "01";
|
IF opcode(10)='0' THEN
|
IF opcode(10)='0' THEN
|
set_movem_busy <='1';
|
set_movem_busy <='1';
|
ELSE
|
ELSE
|
micronext <="00100010";
|
next_micro_state <= movem;
|
microstep <='1';
|
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
|
|
| Line 1819... |
Line 1813... |
ELSE --pea
|
ELSE --pea
|
ea_only <= '1';
|
ea_only <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF nextpass='1' AND prefix='0' THEN
|
IF nextpass='1' AND micro_state=idle THEN
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <="11";
|
setstate <="11";
|
microstep <='1';
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
IF get_ea_now='1' THEN
|
IF get_ea_now='1' THEN
|
setstate <="01";
|
setstate <="01";
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 1874... |
Line 1868... |
-- WHEN "110"=>
|
-- WHEN "110"=>
|
WHEN "111"=> --4EXX
|
WHEN "111"=> --4EXX
|
IF opcode(7)='1' THEN --jsr, jmp
|
IF opcode(7)='1' THEN --jsr, jmp
|
datatype <= "10";
|
datatype <= "10";
|
ea_only <= '1';
|
ea_only <= '1';
|
IF nextpass='1' AND prefix='0' THEN
|
IF nextpass='1' AND micro_state=idle THEN
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <="11";
|
setstate <="11";
|
microstep <='1';
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF get_ea_now='1' THEN --jsr
|
IF get_ea_now='1' THEN --jsr
|
| Line 1904... |
Line 1898... |
trap_trap <='1';
|
trap_trap <='1';
|
trapmake <= '1';
|
trapmake <= '1';
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
datatype <= "10";
|
datatype <= "10";
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
micronext <="01000000";
|
next_micro_state <= link;
|
microstep <='1';
|
|
set_exec_MOVE <= '1'; --für displacement
|
set_exec_MOVE <= '1'; --für displacement
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
source_lowbits <= '1';
|
source_lowbits <= '1';
|
| Line 1992... |
Line 1985... |
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directSR <= '1';
|
set_directSR <= '1';
|
microstep <='1';
|
next_micro_state <= rte;
|
micronext <= "01001000";
|
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
trap_priv <= '1';
|
trap_priv <= '1';
|
trapmake <= '1';
|
trapmake <= '1';
|
END IF;
|
END IF;
|
| Line 2008... |
Line 2000... |
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directPC <= '1';
|
set_directPC <= '1';
|
microstep <='1';
|
next_micro_state <= nop;
|
END IF;
|
END IF;
|
|
|
WHEN "1110110" => --trapv
|
WHEN "1110110" => --trapv
|
IF Flags(1)='1' THEN
|
IF Flags(1)='1' THEN
|
trap_trapv <= '1';
|
trap_trapv <= '1';
|
| Line 2033... |
Line 2025... |
|
|
IF opcode(7 downto 6)="11" THEN --dbcc
|
IF opcode(7 downto 6)="11" THEN --dbcc
|
IF opcode(5 downto 3)="001" THEN --dbcc
|
IF opcode(5 downto 3)="001" THEN --dbcc
|
datatype <= "01"; --Word
|
datatype <= "01"; --Word
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
|
next_micro_state <= nop;
|
OP2out_one <= '1';
|
OP2out_one <= '1';
|
IF condition='0' THEN
|
IF condition='0' THEN
|
Regwrena <= '1';
|
Regwrena <= '1';
|
IF c_in(2)='1' THEN
|
IF c_in(2)='1' THEN
|
micronext <="00011110";
|
next_micro_state <= dbcc1;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
data_is_source <= '1';
|
data_is_source <= '1';
|
microstep <='1';
|
|
END IF;
|
END IF;
|
ELSE --Scc
|
ELSE --Scc
|
datatype <= "00"; --Byte
|
datatype <= "00"; --Byte
|
write_back <= '1';
|
write_back <= '1';
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
| Line 2089... |
Line 2081... |
|
|
-- 0110 ----------------------------------------------------------------------------
|
-- 0110 ----------------------------------------------------------------------------
|
WHEN "0110" => --bra,bsr,bcc
|
WHEN "0110" => --bra,bsr,bcc
|
datatype <= "10";
|
datatype <= "10";
|
|
|
IF prefix='0' THEN
|
IF micro_state=idle THEN
|
IF opcode(11 downto 8)="0001" THEN --bsr
|
IF opcode(11 downto 8)="0001" THEN --bsr
|
IF opcode(7 downto 0)="00000000" THEN
|
IF opcode(7 downto 0)="00000000" THEN
|
micronext <="00011000";
|
next_micro_state <= bsr1;
|
ELSE
|
ELSE
|
micronext <="00011001";
|
next_micro_state <= bsr2;
|
setstate <= "01";
|
setstate <= "01";
|
END IF;
|
END IF;
|
microstep <='1';
|
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
ELSE --bra
|
ELSE --bra
|
IF opcode(7 downto 0)="00000000" THEN
|
IF opcode(7 downto 0)="00000000" THEN
|
microstep <='1';
|
next_micro_state <= bra1;
|
micronext <="00010010";
|
|
END IF;
|
END IF;
|
IF condition='1' THEN
|
IF condition='1' THEN
|
TG68_PC_br8 <= '1';
|
TG68_PC_br8 <= '1';
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
| Line 2133... |
Line 2123... |
WHEN "1000" => --or
|
WHEN "1000" => --or
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
IF (prefix='0' AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
microstep <='1';
|
next_micro_state <= div1;
|
micronext <="10100000";
|
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
|
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
IF (prefix='1' AND nextpass='1') OR execOPC='1' THEN
|
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
ELSE
|
ELSE
|
datatype <= "01";
|
datatype <= "01";
|
END IF;
|
END IF;
|
| Line 2165... |
Line 2154... |
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
presub <= '1';
|
presub <= '1';
|
microstep <='1';
|
next_micro_state <= op_AxAy;
|
micronext <="00110000";
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
| Line 2231... |
Line 2219... |
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
presub <= '1';
|
presub <= '1';
|
microstep <='1';
|
next_micro_state <= op_AxAy;
|
micronext <="00110000";
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
| Line 2287... |
Line 2274... |
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
postadd <= '1';
|
postadd <= '1';
|
microstep <='1';
|
next_micro_state <= cmpm;
|
micronext <="00110010";
|
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
setaddsub <= '0';
|
setaddsub <= '0';
|
END IF;
|
END IF;
|
| Line 2328... |
Line 2314... |
WHEN "1100" => --and, exg
|
WHEN "1100" => --and, exg
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
regdirectsource <= '1';
|
regdirectsource <= '1';
|
END IF;
|
END IF;
|
IF (prefix='0' AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
microstep <='1';
|
next_micro_state <= mul1;
|
micronext <="10000000";
|
|
END IF;
|
END IF;
|
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
regwrena <= '1';
|
regwrena <= '1';
|
END IF;
|
END IF;
|
IF (prefix='1' AND nextpass='1') OR execOPC='1' THEN
|
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
source_lowbits <='1';
|
source_lowbits <='1';
|
ELSE
|
ELSE
|
datatype <= "01";
|
datatype <= "01";
|
END IF;
|
END IF;
|
| Line 2360... |
Line 2345... |
IF decodeOPC='1' THEN
|
IF decodeOPC='1' THEN
|
set_direct_data <= '1';
|
set_direct_data <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
presub <= '1';
|
presub <= '1';
|
microstep <='1';
|
next_micro_state <= op_AxAy;
|
micronext <="00110000";
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF execOPC='1' THEN
|
IF execOPC='1' THEN
|
ea_data_OP1 <= '1';
|
ea_data_OP1 <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
| Line 2467... |
Line 2451... |
-- END PROCESS;
|
-- END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- execute microcode
|
-- execute microcode
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
--PROCESS (microaddr)
|
--PROCESS (micro_state)
|
-- BEGIN
|
-- BEGIN
|
IF Z_error='1' THEN -- divu by zero
|
IF Z_error='1' THEN -- divu by zero
|
trapmake <= '1'; --wichtig für USP
|
trapmake <= '1'; --wichtig für USP
|
IF trapd='0' THEN
|
IF trapd='0' THEN
|
writePC <= '1';
|
writePC <= '1';
|
microset <= '1';
|
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
|
|
IF trapmake='1' AND trapd='0' THEN
|
IF trapmake='1' AND trapd='0' THEN
|
microstep <= '1';
|
next_micro_state <= trap1;
|
micronext <= "01010000";
|
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "10";
|
datatype <= "10";
|
END IF;
|
END IF;
|
|
|
IF interrupt='1' THEN
|
IF interrupt='1' THEN
|
microstep <= '1';
|
next_micro_state <= int1;
|
micronext <= "01000100";
|
|
setstate <= "10";
|
setstate <= "10";
|
-- datatype <= "01"; --wirkt sich auf Flags aus
|
-- datatype <= "01"; --wirkt sich auf Flags aus
|
END IF;
|
END IF;
|
|
|
|
|
IF reset='0' THEN
|
IF reset='0' THEN
|
microaddr <= "01100000"; --init
|
micro_state <= init1;
|
prefix <= '1';
|
|
ELSIF rising_edge(clk) THEN
|
ELSIF rising_edge(clk) THEN
|
IF clkena='1' THEN
|
IF clkena='1' THEN
|
trapd <= trapmake;
|
trapd <= trapmake;
|
prefix <= (prefix AND ea_build) OR (microstep AND NOT fetchOPC);
|
IF fetchOPC='1' THEN
|
IF prefix='1' AND ea_build='0' AND microset='0' THEN
|
micro_state <= idle;
|
microaddr <= microaddr + micronext;
|
|
ELSE
|
ELSE
|
microaddr <= micronext;
|
micro_state <= next_micro_state;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
IF prefix='1' THEN
|
CASE micro_state IS
|
CASE microaddr IS
|
WHEN ld_nn => -- (nnnn).w/l=>
|
WHEN "00000001" => -- nop
|
|
|
|
WHEN "00000010" => -- (nnnn).w/l=>
|
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
setaddrlong <= '1';
|
setaddrlong <= '1';
|
|
|
WHEN "00000011" => -- =>(nnnn).w/l
|
WHEN st_nn => -- =>(nnnn).w/l
|
setstate <= "11";
|
setstate <= "11";
|
setaddrlong <= '1';
|
setaddrlong <= '1';
|
microstep <='1';
|
next_micro_state <= nop;
|
|
|
WHEN "00000110" => -- d(An)=>, --d(PC)=>
|
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
WHEN "00000111" => -- d(An)=>, --d(PC)=>
|
next_micro_state <= ld_dAn2;
|
|
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setdisp <= '1'; --word
|
setdisp <= '1'; --word
|
setnextpass <= '1';
|
setnextpass <= '1';
|
|
|
WHEN "00001000" => -- d(An,Xn)=>, --d(PC,Xn)=>
|
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
WHEN "00001001" => -- d(An,Xn)=>, --d(PC,Xn)=>
|
next_micro_state <= ld_AnXn2;
|
|
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
|
setdisp <= '1'; --byte
|
setdisp <= '1'; --byte
|
setdispbyte <= '1';
|
setdispbyte <= '1';
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
setbriefext <= '1';
|
setbriefext <= '1';
|
WHEN "00001010" =>
|
next_micro_state <= ld_AnXn3;
|
|
WHEN ld_AnXn3 =>
|
get_ea_now <='1';
|
get_ea_now <='1';
|
setdisp <= '1'; --brief
|
setdisp <= '1'; --brief
|
setdispbrief <= '1';
|
setdispbrief <= '1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
|
|
WHEN "00001011" => -- =>d(An)
|
WHEN st_dAn1 => -- =>d(An)
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
WHEN "00001100" => -- =>d(An)
|
next_micro_state <= st_dAn2;
|
|
WHEN st_dAn2 => -- =>d(An)
|
setstate <= "11";
|
setstate <= "11";
|
setdisp <= '1'; --word
|
setdisp <= '1'; --word
|
microstep <='1';
|
next_micro_state <= nop;
|
WHEN "00001101" =>
|
|
|
|
WHEN "00001110" => -- =>d(An,Xn)
|
WHEN st_AnXn1 => -- =>d(An,Xn)
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
WHEN "00001111" => -- =>d(An,Xn)
|
next_micro_state <= st_AnXn2;
|
|
WHEN st_AnXn2 => -- =>d(An,Xn)
|
setdisp <= '1'; --byte
|
setdisp <= '1'; --byte
|
setdispbyte <= '1';
|
setdispbyte <= '1';
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
setbriefext <= '1';
|
setbriefext <= '1';
|
WHEN "00010000" =>
|
next_micro_state <= st_AnXn3;
|
|
WHEN st_AnXn3 =>
|
setstate <= "11";
|
setstate <= "11";
|
setdisp <= '1'; --brief
|
setdisp <= '1'; --brief
|
setdispbrief <= '1';
|
setdispbrief <= '1';
|
microstep <='1';
|
next_micro_state <= nop;
|
WHEN "00010001" =>
|
|
|
|
WHEN "00010010" => --bra
|
WHEN bra1 => --bra
|
IF condition='1' THEN
|
IF condition='1' THEN
|
TG68_PC_br8 <= '1'; --pc+0000
|
TG68_PC_br8 <= '1'; --pc+0000
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
|
next_micro_state <= bra2;
|
END IF;
|
END IF;
|
WHEN "00010011" => --bra
|
WHEN bra2 => --bra
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
|
|
WHEN "00011000" => --bsr
|
WHEN bsr1 => --bsr
|
set_TG68_PC_dec <= '1'; --in 2 Takten -2
|
set_TG68_PC_dec <= '1'; --in 2 Takten -2
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
WHEN "00011001" => --bsr
|
next_micro_state <= bsr2;
|
|
WHEN bsr2 => --bsr
|
IF TG68_PC_dec(0)='1' THEN
|
IF TG68_PC_dec(0)='1' THEN
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
ELSE
|
ELSE
|
TG68_PC_br8 <= '1';
|
TG68_PC_br8 <= '1';
|
END IF;
|
END IF;
|
writePC <= '1';
|
writePC <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
microstep <='1';
|
next_micro_state <= nop;
|
WHEN "00011010" => --bsr
|
|
|
|
WHEN "00011110" => --dbcc
|
WHEN dbcc1 => --dbcc
|
TG68_PC_nop <= '1';
|
TG68_PC_nop <= '1';
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
WHEN "00011111" => --dbcc
|
next_micro_state <= dbcc2;
|
|
WHEN dbcc2 => --dbcc
|
TG68_PC_brw <= '1';
|
TG68_PC_brw <= '1';
|
|
|
WHEN "00100010" => --movem
|
WHEN movem => --movem
|
set_movem_busy <='1';
|
set_movem_busy <='1';
|
setstate <= "10";
|
setstate <= "10";
|
|
|
WHEN "00101000" => --andi
|
WHEN andi => --andi
|
IF opcode(5 downto 4)/="00" THEN
|
IF opcode(5 downto 4)/="00" THEN
|
ea_build <= '1';
|
ea_build <= '1';
|
setnextpass <= '1';
|
setnextpass <= '1';
|
END IF;
|
END IF;
|
|
|
WHEN "00101100" => --jsr
|
WHEN op_AxAy => -- op -(Ax),-(Ay)
|
presub <= '1';
|
|
setstackaddr <='1';
|
|
set_mem_addsub <= '1';
|
|
setstate <= "11";
|
|
|
|
WHEN "00110000" => -- op -(Ax),-(Ay)
|
|
presub <= '1';
|
presub <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
dest_areg <= '1';
|
dest_areg <= '1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
|
|
WHEN "00110010" => -- cmpm (Ay)+,(Ax)+
|
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
|
postadd <= '1';
|
postadd <= '1';
|
dest_hbits <= '1';
|
dest_hbits <= '1';
|
dest_areg <= '1';
|
dest_areg <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
|
|
WHEN "01000000" => -- link
|
WHEN link => -- link
|
setstate <="11";
|
setstate <="11";
|
save_memaddr <= '1';
|
save_memaddr <= '1';
|
regwrena <= '1';
|
regwrena <= '1';
|
|
|
WHEN "01000100" => -- interrupt
|
WHEN int1 => -- interrupt
|
microstep <= '1';
|
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "10";
|
datatype <= "10";
|
WHEN "01000101" => -- interrupt
|
next_micro_state <= int2;
|
microstep <= '1';
|
WHEN int2 => -- interrupt
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "01";
|
datatype <= "01";
|
writeSR <= '1';
|
writeSR <= '1';
|
WHEN "01000110" => -- interrupt
|
next_micro_state <= int3;
|
|
WHEN int3 => -- interrupt
|
set_vectoraddr <= '1';
|
set_vectoraddr <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
set_directPC <= '1';
|
set_directPC <= '1';
|
microstep <='1';
|
|
|
|
setstate <= "10";
|
setstate <= "10";
|
WHEN "01000111" => -- interrupt
|
next_micro_state <= int4;
|
|
WHEN int4 => -- interrupt
|
datatype <= "10";
|
datatype <= "10";
|
|
|
WHEN "01001000" => -- RTE
|
WHEN rte => -- RTE
|
datatype <= "10";
|
datatype <= "10";
|
setstate <= "10";
|
setstate <= "10";
|
postadd <= '1';
|
postadd <= '1';
|
setstackaddr <= '1';
|
setstackaddr <= '1';
|
set_mem_rega <= '1';
|
set_mem_rega <= '1';
|
set_directPC <= '1';
|
set_directPC <= '1';
|
microstep <='1';
|
next_micro_state <= nop;
|
|
|
WHEN "01010000" => -- TRAP
|
WHEN trap1 => -- TRAP
|
microstep <= '1';
|
|
presub <= '1';
|
presub <= '1';
|
setstackaddr <='1';
|
setstackaddr <='1';
|
set_mem_addsub <= '1';
|
set_mem_addsub <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
datatype <= "01";
|
datatype <= "01";
|
writeSR <= '1';
|
writeSR <= '1';
|
WHEN "01010001" => -- TRAP
|
next_micro_state <= trap2;
|
|
WHEN trap2 => -- TRAP
|
set_vectoraddr <= '1';
|
set_vectoraddr <= '1';
|
datatype <= "10";
|
datatype <= "10";
|
set_directPC <= '1';
|
set_directPC <= '1';
|
microstep <='1';
|
|
-- longreaddirect <= '1';
|
-- longreaddirect <= '1';
|
setstate <= "10";
|
setstate <= "10";
|
WHEN "01010010" => -- TRAP
|
next_micro_state <= trap3;
|
|
WHEN trap3 => -- TRAP
|
datatype <= "10";
|
datatype <= "10";
|
|
|
WHEN "01010110" => -- MOVEP d(An)
|
WHEN movep1 => -- MOVEP d(An)
|
microstep <='1';
|
|
setstate <= "01";
|
setstate <= "01";
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
set_movepl <= '1';
|
set_movepl <= '1';
|
END IF;
|
END IF;
|
WHEN "01010111" =>
|
next_micro_state <= movep2;
|
microstep <='1';
|
WHEN movep2 =>
|
setdisp <= '1';
|
setdisp <= '1';
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
setstate <= "11";
|
setstate <= "11";
|
wait_mem_byte <= '1';
|
wait_mem_byte <= '1';
|
END IF;
|
END IF;
|
WHEN "01011000" =>
|
next_micro_state <= movep3;
|
|
WHEN movep3 =>
|
IF opcode(6)='1' THEN
|
IF opcode(6)='1' THEN
|
microstep <='1';
|
|
set_movepw <= '1';
|
set_movepw <= '1';
|
|
next_micro_state <= movep4;
|
END IF;
|
END IF;
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
setstate <= "11";
|
setstate <= "11";
|
END IF;
|
END IF;
|
WHEN "01011001" =>
|
WHEN movep4 =>
|
microstep <='1';
|
|
|
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
wait_mem_byte <= '1';
|
wait_mem_byte <= '1';
|
setstate <= "11";
|
setstate <= "11";
|
END IF;
|
END IF;
|
WHEN "01011010" =>
|
next_micro_state <= movep5;
|
|
WHEN movep5 =>
|
IF opcode(7)='0' THEN
|
IF opcode(7)='0' THEN
|
setstate <= "10";
|
setstate <= "10";
|
ELSE
|
ELSE
|
setstate <= "11";
|
setstate <= "11";
|
END IF;
|
END IF;
|
|
|
|
WHEN init1 => -- init SP
|
|
|
|
|
|
|
WHEN "01100000" => -- init SP
|
|
microstep <='1';
|
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
WHEN "01100001" => -- init PC
|
next_micro_state <= init2;
|
|
WHEN init2 => -- init PC
|
get_ea_now <='1'; --\
|
get_ea_now <='1'; --\
|
ea_only <= '1'; --- OP1in <= memaddr_in
|
ea_only <= '1'; --- OP1in <= memaddr_in
|
setaddrlong <= '1'; -- memaddr_in <= data_read
|
setaddrlong <= '1'; -- memaddr_in <= data_read
|
regwrena <= '1';
|
regwrena <= '1';
|
setstackaddr <='1'; -- dest_addr <= SP
|
setstackaddr <='1'; -- dest_addr <= SP
|
set_directPC <= '1';
|
set_directPC <= '1';
|
microstep <='1';
|
|
longreaddirect <= '1';
|
longreaddirect <= '1';
|
-- WHEN "01100010" => -- wr SP
|
next_micro_state <= nop;
|
|
|
|
|
|
|
|
WHEN mul1 => -- mulu
|
WHEN "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|
|
|
"10000111"|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101" => -- mulu
|
|
microstep <='1';
|
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
setstate <="01";
|
setstate <="01";
|
WHEN "10001110" => -- mulu
|
next_micro_state <= mul2;
|
|
WHEN mul2 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul3;
|
|
WHEN mul3 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul4;
|
|
WHEN mul4 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul5;
|
|
WHEN mul5 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul6;
|
|
WHEN mul6 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul7;
|
|
WHEN mul7 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul8;
|
|
WHEN mul8 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul9;
|
|
WHEN mul9 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul10;
|
|
WHEN mul10 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul11;
|
|
WHEN mul11 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul12;
|
|
WHEN mul12 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul13;
|
|
WHEN mul13 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul14;
|
|
WHEN mul14 => -- mulu
|
|
set_exec_MULU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= mul15;
|
|
WHEN mul15 => -- mulu
|
set_exec_MULU <= '1';
|
set_exec_MULU <= '1';
|
|
|
|
WHEN div1 => -- divu
|
WHEN "10100000" => -- divu
|
|
IF OP2out(15 downto 0)=x"0000" THEN --div zero
|
IF OP2out(15 downto 0)=x"0000" THEN --div zero
|
set_Z_error <= '1';
|
set_Z_error <= '1';
|
microset <= '1';
|
|
ELSE
|
ELSE
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
|
next_micro_state <= div2;
|
END IF;
|
END IF;
|
setstate <="01";
|
setstate <="01";
|
microstep <='1';
|
WHEN div2 => -- divu
|
WHEN "10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100110"|"10100111"|
|
|
"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101" => -- divu
|
|
microstep <='1';
|
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
setstate <="01";
|
setstate <="01";
|
WHEN "10101110" => -- divu
|
next_micro_state <= div3;
|
|
WHEN div3 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div4;
|
|
WHEN div4 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div5;
|
|
WHEN div5 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div6;
|
|
WHEN div6 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div7;
|
|
WHEN div7 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div8;
|
|
WHEN div8 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div9;
|
|
WHEN div9 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div10;
|
|
WHEN div10 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div11;
|
|
WHEN div11 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div12;
|
|
WHEN div12 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div13;
|
|
WHEN div13 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div14;
|
|
WHEN div14 => -- divu
|
|
set_exec_DIVU <= '1';
|
|
setstate <="01";
|
|
next_micro_state <= div15;
|
|
WHEN div15 => -- divu
|
set_exec_DIVU <= '1';
|
set_exec_DIVU <= '1';
|
|
|
|
|
WHEN OTHERS => null;
|
WHEN OTHERS => null;
|
END CASE;
|
END CASE;
|
END IF;
|
|
END PROCESS;
|
END PROCESS;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Conditions
|
-- Conditions
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
