URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [Collaterals/] [Module_RadixRMul.v] - Diff between revs 39 and 70

Rev 39	Rev 70
Line 76...	Line 76...

`);`	`);`


`wire wInputDelay1;`	`wire wInputDelay1;`
	`//-------------------`
	`wire [31:0] wALatched,wBLatched;`
	FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD1
	`(`
	`.Clock( Clock ),`
	`.Reset( Reset),`
	`.Enable( iInputReady ),`
	`.D( A ),`
	`.Q( wALatched)`
	`);`
	FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD2
	`(`
	`.Clock( Clock ),`
	`.Reset( Reset),`
	`.Enable( iInputReady ),`
	`.D( B ),`
	`.Q( wBLatched )`
	`);`

	`//-------------------`


`FFD_POSEDGE_ASYNC_RESET #(1) FFOutputReadyDelay1`	`FFD_POSEDGE_ASYNC_RESET #(1) FFOutputReadyDelay1`
`(`	`(`
`.Clock( Clock ),`	`.Clock( Clock ),`
`.Clear( Reset ),`	`.Clear( Reset ),`
Line 96...	Line 117...
`);`	`);`

`wire [31:0] wA, w2A, w3A, wB;`	`wire [31:0] wA, w2A, w3A, wB;`
`wire SignA,SignB;`	`wire SignA,SignB;`

`assign SignA = A[31];`	`assign SignA = wALatched[31];`
`assign SignB = B[31];`	`assign SignB = wBLatched[31];`


`assign wB = (SignB == 1) ? ~B + 1'b1 : B;`	`assign wB = (SignB == 1) ? ~wBLatched + 1'b1 : wBLatched;`
`assign wA = (SignA == 1) ? ~A + 1'b1 : A;`	`assign wA = (SignA == 1) ? ~wALatched + 1'b1 : wALatched;`

`assign w2A = wA << 1;`	`assign w2A = wA << 1;`
`assign w3A = w2A + wA;`	`assign w3A = w2A + wA;`

`wire [31:0] wPartialResult0,wPartialResult1,wPartialResult2,wPartialResult3,wPartialResult4,wPartialResult5;`	`wire [31:0] wPartialResult0,wPartialResult1,wPartialResult2,wPartialResult3,wPartialResult4,wPartialResult5;`