| Line 47... |
Line 47... |
output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
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output wire oInstructionWriteEnable,
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output wire oInstructionWriteEnable,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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inout wire [`WIDTH-1:0] oData,
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inout wire [`WIDTH-1:0] oData,
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output wire oBusy,
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output wire oDone,
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output wire oDone,
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//Theia specific interfaces
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//Theia specific interfaces
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input wire MST_I,
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input wire MST_I,
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//Wish Bone Interfaces
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//Wish Bone Interfaces
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output wire [31:0] DAT_O,
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output wire [31:0] DAT_O,
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| Line 93... |
Line 94... |
wire[`WIDTH-1:0] wWBS_2__WBMToMEM_Address;
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wire[`WIDTH-1:0] wWBS_2__WBMToMEM_Address;
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wire wWBSToMEM2__oDataWriteEnable;
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wire wWBSToMEM2__oDataWriteEnable;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
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assign oBusy = CYC_O;
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wire wReadOperation;
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wire wReadOperation;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
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assign wMEMToWBM_2__Address = ( iAdr_O_Type == `ADR_IMM ) ? iAdr_O_Imm : wMEMToWBM2__ReadDataElement;
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assign wMEMToWBM_2__Address = ( iAdr_O_Type == `ADR_IMM ) ? iAdr_O_Imm : wMEMToWBM2__ReadDataElement;
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