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[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [MEM/] [Module_RAM.v] - Diff between revs 20 and 60

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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
 
***********************************************************************************/
***********************************************************************************/
//--------------------------------------------------------
//--------------------------------------------------------
//Dual port RAM.
//Dual port RAM.
//Each Row has 3* 32 bit entries (x,y and Z)
 
 
 
module RAM_DATA
 
 
module RAM_128_ROW_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH )
(
(
        input wire                                                                      Clock,
        input wire                                                                      Clock,
        input wire                                                                      iWriteEnable,
        input wire                                                                      iWriteEnable,
        input wire[`DATA_ADDRESS_WIDTH-1:0]      iReadAddress0,
        input wire[ADDR_WIDTH-1:0]       iReadAddress0,
        input wire[`DATA_ADDRESS_WIDTH-1:0]      iReadAddress1,
        input wire[ADDR_WIDTH-1:0]       iReadAddress1,
        input wire[`DATA_ADDRESS_WIDTH-1:0]      iWriteAddress,
        input wire[ADDR_WIDTH-1:0]       iWriteAddress,
        input wire[`DATA_ROW_WIDTH-1:0]                  iDataIn,
        input wire[DATA_WIDTH-1:0]                       iDataIn,
        output reg [`DATA_ROW_WIDTH-1:0]                 oDataOut0,
        output reg [DATA_WIDTH-1:0]              oDataOut0,
        output reg [`DATA_ROW_WIDTH-1:0]                 oDataOut1
        output reg [DATA_WIDTH-1:0]              oDataOut1
);
);
 
 
reg [`DATA_ROW_WIDTH-1:0] Ram [128:0];
reg [DATA_WIDTH-1:0] Ram [128:0];
 
 
always @(posedge Clock)
always @(posedge Clock)
begin
begin
 
 
                if (iWriteEnable)
                if (iWriteEnable)
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                        oDataOut1 <= Ram[iReadAddress1];
                        oDataOut1 <= Ram[iReadAddress1];
 
 
end
end
endmodule
endmodule
//--------------------------------------------------------
//--------------------------------------------------------
//Single port RAM.
 
module RAM_INST
 
(
 
        input wire                                                                      Clock,
 
        input wire                                                                      iWriteEnable,
 
        input wire[`DATA_ADDRESS_WIDTH-1:0]      iReadAddress,
 
        input wire[`DATA_ADDRESS_WIDTH-1:0]      iWriteAddress,
 
        input wire[`INSTRUCTION_WIDTH-1:0]                       iDataIn,
 
        output reg [`INSTRUCTION_WIDTH-1:0]              oDataOut
 
 
 
);
 
 
 
reg [`INSTRUCTION_WIDTH-1:0] Ram [128:0];
 
 
 
always @(posedge Clock)
 
begin
 
 
 
                if (iWriteEnable)
 
                        Ram[iWriteAddress] <= iDataIn;
 
 
 
                oDataOut <= Ram[iReadAddress];
 
 
 
 
 
end
 
endmodule
 
//--------------------------------------------------------
 
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