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Rev 74 |
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***********************************************************************************/
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***********************************************************************************/
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//--------------------------------------------------------
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//--------------------------------------------------------
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//Dual port RAM.
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//Dual port RAM.
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module RAM_128_ROW_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH )
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module RAM_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 )
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(
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(
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input wire Clock,
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input wire Clock,
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input wire iWriteEnable,
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input wire iWriteEnable,
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input wire[ADDR_WIDTH-1:0] iReadAddress0,
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input wire[ADDR_WIDTH-1:0] iReadAddress0,
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input wire[ADDR_WIDTH-1:0] iReadAddress1,
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input wire[ADDR_WIDTH-1:0] iReadAddress1,
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input wire[DATA_WIDTH-1:0] iDataIn,
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input wire[DATA_WIDTH-1:0] iDataIn,
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output reg [DATA_WIDTH-1:0] oDataOut0,
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output reg [DATA_WIDTH-1:0] oDataOut0,
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output reg [DATA_WIDTH-1:0] oDataOut1
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output reg [DATA_WIDTH-1:0] oDataOut1
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);
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);
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reg [DATA_WIDTH-1:0] Ram [128:0];
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reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0];
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always @(posedge Clock)
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always @(posedge Clock)
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begin
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begin
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if (iWriteEnable)
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if (iWriteEnable)
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