| Line 46... |
Line 46... |
wire [1:0] wBusSelect;
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wire [1:0] wBusSelect;
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//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
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//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
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//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
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//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
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wire [`MAX_CORES-1:0] wSTB_O,wWE_O;
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wire [`MAX_CORES-1:0] wSTB_O,wWE_O,wACK_O;
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wire wACK_O_0,wACK_O_1,wACK_O_2,wACK_O_3;
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wire [`MAX_CORES-1:0] wSTB_I;
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wire [`MAX_CORES-1:0] wSTB_I;
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wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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//assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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//assign DONE_O = wDone[1];
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//assign DONE_O = wDone[0];
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assign DONE_O = wDone[0] & wDone[1];
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//assign DONE_O = wDone[0] & wDone[1];// & wDone[2];
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// assign wDone[3:1] = 3'b111;
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// assign wDone[3:1] = 3'b111;
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assign wBusRequest[3:2] = 0;
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// assign wBusRequest[3:2] = 0;
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assign wSTB_O[3:2] = 0;
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// assign wSTB_O[3:2] = 0;
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assign wWE_O[3:2] = 0;
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// assign wWE_O[3:2] = 0;
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Module_BusArbitrer ARB1
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Module_BusArbitrer ARB1
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(
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(
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.Clock( CLK_I ),
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.Clock( CLK_I ),
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.Reset( RST_I ),
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.Reset( RST_I ),
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.iRequest( wBusRequest ),
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.iRequest( wBusRequest ),
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| Line 132... |
Line 131... |
.I4(wTGA_O_3),
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.I4(wTGA_O_3),
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.O1( TGA_O )
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.O1( TGA_O )
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);
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);
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assign ACK_O = (wACK_O_0 | wACK_O_1);// | wACK_O_2 | wACK_O_3);
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assign ACK_O = (wACK_O[0] | wACK_O[1] | wACK_O[2] | wACK_O[3]);
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assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
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assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
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assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
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assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
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assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
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assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
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assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
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assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
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| Line 155... |
Line 154... |
assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
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assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
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assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
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assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
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assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
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assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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wire foo;
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assign foo = ACK_I;
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THEIACORE THEIA_CORE0
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THEIACORE THEIA_CORE0
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(
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(
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.CLK_I( CLK_I ),
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[0] ),
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.RENDREN_I( RENDREN_I[0] ),
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| Line 170... |
Line 168... |
.WE_I( WE_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[0] ),
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.STB_I( wSTB_I[0] ),
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//-----------------------------------
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//-----------------------------------
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//This signal behaves in a very funny way...
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//This signal behaves in a very funny way...
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//
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//
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.ACK_I( ACK_I ),//& wBusGranted[0] ),//wACK_I[0] ), //WTF??? ok I think it works fine like this...
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.ACK_I( ACK_I ),
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//-----------------------------------
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//-----------------------------------
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.CYC_I( wCYC_I[0] ),
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.CYC_I( wCYC_I[0] ),
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.MST_I( wMST_I[0] ),
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.MST_I( wMST_I[0] ),
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.TGA_I( wTGA_I[0] ),
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.TGA_I( wTGA_I[0] ),
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.CREG_I( CREG_I ),
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.CREG_I( CREG_I ),
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//Master Signals
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//Master Signals
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.WE_O ( wWE_O[0] ),
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.WE_O ( wWE_O[0] ),
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.STB_O( wSTB_O[0] ),
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.STB_O( wSTB_O[0] ),
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.ACK_O( wACK_O_0 ),
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.ACK_O( wACK_O[0] ),
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.DAT_O( wDAT_O_0 ),
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.DAT_O( wDAT_O_0 ),
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.ADR_O( wADR_O_0 ),
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.ADR_O( wADR_O_0 ),
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.CYC_O( wBusRequest[0] ),
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.CYC_O( wBusRequest[0] ),
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.GNT_I( wBusGranted[0] ),
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.GNT_I( wBusGranted[0] ),
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.TGA_O( wTGA_O_0 ),
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.TGA_O( wTGA_O_0 ),
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| Line 205... |
Line 203... |
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//Slave signals
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//Slave signals
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.ADR_I( ADR_I ),
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[1] ),//ok
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.STB_I( wSTB_I[1] ),//ok
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.ACK_I( ACK_I ),//& wBusGranted[1] ),//wACK_I[0] ), //WTF??? ok I think it works fine like this...
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.ACK_I( ACK_I ),
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.CYC_I( wCYC_I[1] ),//ok
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.CYC_I( wCYC_I[1] ),//ok
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.MST_I( wMST_I[1] ),//ok
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.MST_I( wMST_I[1] ),//ok
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.TGA_I( wTGA_I[1] ),//ok
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.TGA_I( wTGA_I[1] ),//ok
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.CREG_I( CREG_I ),
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.CREG_I( CREG_I ),
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//Master Signals
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//Master Signals
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.WE_O ( wWE_O[1] ),
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.WE_O ( wWE_O[1] ),
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.STB_O( wSTB_O[1] ),
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.STB_O( wSTB_O[1] ),
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.ACK_O( wACK_O_1 ),
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.ACK_O( wACK_O[1] ),
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.DAT_O( wDAT_O_1 ),
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.DAT_O( wDAT_O_1 ),
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.ADR_O( wADR_O_1 ),
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.ADR_O( wADR_O_1 ),
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.CYC_O( wBusRequest[1] ),
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.CYC_O( wBusRequest[1] ),
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.GNT_I( wBusGranted[1] ),
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.GNT_I( wBusGranted[1] ),
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.TGA_O( wTGA_O_1 ),
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.TGA_O( wTGA_O_1 ),
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| Line 229... |
Line 227... |
.DAT_I( DAT_I ),
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.DAT_I( DAT_I ),
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.DONE_O( wDone[1] )
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.DONE_O( wDone[1] )
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|
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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THEIACORE THEIA_CORE2
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(
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[2] ),
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//Slave signals
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[2] ),
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.ACK_I( ACK_I ),
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.CYC_I( wCYC_I[2] ),
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.MST_I( wMST_I[2] ),
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.TGA_I( wTGA_I[2] ),
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.CREG_I( CREG_I ),
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//Master Signals
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.WE_O ( wWE_O[2] ),
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.STB_O( wSTB_O[2] ),
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.ACK_O( wACK_O[2] ),
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.DAT_O( wDAT_O_2 ),
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.ADR_O( wADR_O_2 ),
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.CYC_O( wBusRequest[2] ),
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.GNT_I( wBusGranted[2] ),
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.TGA_O( wTGA_O_2 ),
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`ifdef DEBUG
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.iDebug_CoreID( `MAX_CORES'd2 ),
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`endif
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//Other
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.DAT_I( DAT_I ),
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.DONE_O( wDone[2] )
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|
|
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);
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//----------------------------------------------------------------
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THEIACORE THEIA_CORE3
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(
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[3] ),
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//Slave signals
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[3] ),
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.ACK_I( ACK_I ),
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.CYC_I( wCYC_I[3] ),
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.MST_I( wMST_I[3] ),
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.TGA_I( wTGA_I[3] ),
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.CREG_I( CREG_I ),
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//Master Signals
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.WE_O ( wWE_O[3] ),
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.STB_O( wSTB_O[3] ),
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.ACK_O( wACK_O[3] ),
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.DAT_O( wDAT_O_3 ),
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.ADR_O( wADR_O_3 ),
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.CYC_O( wBusRequest[3] ),
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.GNT_I( wBusGranted[3] ),
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.TGA_O( wTGA_O_3 ),
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`ifdef DEBUG
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.iDebug_CoreID( `MAX_CORES'd3 ),
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`endif
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//Other
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.DAT_I( DAT_I ),
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.DONE_O( wDone[3] )
|
|
|
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);
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//----------------------------------------------------------------
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endmodule
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endmodule
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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