| Line 145... |
Line 145... |
end
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end
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|
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endmodule
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endmodule
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|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
module DECODER_ONEHOT_2_BINARY
|
|
|
module DECODER_ONEHOT_2_BINARY # (parameter OUTPUT_WIDTH = 6)
|
(
|
(
|
input wire [5:0] iIn,
|
input wire [6:0] iIn,
|
output reg[5:0] oOut
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output reg[OUTPUT_WIDTH-1:0] oOut
|
);
|
);
|
|
|
always @ (*)
|
always @ (*)
|
begin
|
begin
|
case (iIn)
|
case (iIn)
|
6'b000000: oOut = 0;
|
7'b0000000: oOut = 0;
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6'b000001: oOut = 1;
|
7'b0000001: oOut = 1;
|
6'b000010: oOut = 2;
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7'b0000010: oOut = 2;
|
6'b000100: oOut = 3;
|
7'b0000100: oOut = 3;
|
6'b001000: oOut = 4;
|
7'b0001000: oOut = 4;
|
6'b010000: oOut = 5;
|
7'b0010000: oOut = 5;
|
6'b100000: oOut = 6;
|
7'b0100000: oOut = 6;
|
|
7'b1000000: oOut = 7;
|
default:
|
default:
|
oOut = 0;
|
oOut = 0;
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
endmodule
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
|
|
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
|
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
|
(
|
(
|
input wire [SEL_WIDTH-1:0] Sel,
|
input wire [SEL_WIDTH-1:0] Sel,
|
| Line 1056... |
Line 1059... |
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
|
|
assign oPriorityGrant = wGrant0;
|
assign oPriorityGrant = wGrant0;
|
|
wire wGrant1_Pre, wGrant2_Pre, wGrant3_Pre, wGrant4_Pre;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
|
( Clock, Reset, 1'b1 , wGrant1, wGrant1_Pre ); //If priority grant comes this cycle then we are having troubles...
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
|
( Clock, Reset, 1'b1 , wGrant2, wGrant2_Pre );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
|
( Clock, Reset, 1'b1 , wGrant3, wGrant3_Pre );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
|
( Clock, Reset, 1'b1 , wGrant4, wGrant4_Pre );
|
|
|
|
|
|
|
|
assign oGrant1 = wGrant1_Pre & ~oPriorityGrant;
|
|
assign oGrant2 = wGrant2_Pre & ~oPriorityGrant;
|
|
assign oGrant3 = wGrant3_Pre & ~oPriorityGrant;
|
|
assign oGrant4 = wGrant4_Pre & ~oPriorityGrant;
|
|
|
reg [4:0] rCurrentState, rNextState;
|
reg [4:0] rCurrentState, rNextState;
|
//Next states logic and Reset sequence
|
//Next states logic and Reset sequence
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
| Line 1096... |
Line 1103... |
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
case (rCurrentState)
|
case (rCurrentState)
|
//--------------------------------------
|
//--------------------------------------
|
0:
|
0: //Mask for grant 0
|
begin
|
begin
|
rMask = 3'd0;
|
rMask = 3'd0;
|
rNextState = 1;
|
rNextState = 1;
|
end
|
end
|
1:
|
1: //Mask for grant 1
|
begin
|
begin
|
rMask = 3'd1;
|
rMask = 3'd1;
|
rNextState = 2;
|
rNextState = 2;
|
end
|
end
|
2:
|
2:
|
