| Line 95... |
Line 95... |
wire wReservationStationBusy;
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wire wReservationStationBusy;
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wire [`COMMIT_PACKET_SIZE-1:0] wResultFifoData;
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wire [`COMMIT_PACKET_SIZE-1:0] wResultFifoData;
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reg rTagMemoryWE,rTagMemOwner,rIssueNow,rIncrementPC,rPopFifo,rBypassFifo,rUseForwardedData;
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reg rTagMemoryWE,rTagMemOwner,rIssueNow,rIncrementPC,rPopFifo,rBypassFifo,rUseForwardedData;
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reg rSetPCBranchTaken;
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reg rSetPCBranchTaken;
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wire wBranchWithDependency;
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wire wBranchWithDependency;
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wire wIO_Operation_TMWRITE;
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wire wMtHasOnceMoreTimeSlot,wEnabled_Delay;
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wire wMtHasOnceMoreTimeSlot,wEnabled_Delay;
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wire wIO_Operation;
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wire wIO_Operation;
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assign wIO_Operation = (~wOp[0] & wOp[1] & wOp[2] & ~wOp[3]);
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assign wIO_Operation = (~wOp[0] & wOp[1] & wOp[2] & ~wOp[3]);
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assign wIO_Operation_TMWRITE = wIO_Operation && (iInstruction0[`INST_SCOP_RNG] == `IO_OPERATION_OMWRITE);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD123
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD123
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( Clock, Reset, 1'b1 , iEnable , wEnabled_Delay );
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( Clock, Reset, 1'b1 , iEnable , wEnabled_Delay );
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assign wMtHasOnceMoreTimeSlot = ~wEnabled_Delay;
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assign wMtHasOnceMoreTimeSlot = ~wEnabled_Delay;
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| Line 145... |
Line 150... |
/*The PC will be incremented except for the scenario where we need to wait
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/*The PC will be incremented except for the scenario where we need to wait
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for reservation stations to become available. If we increment the PC, then the
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for reservation stations to become available. If we increment the PC, then the
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value of PC will get update the next clock cycle, and another clock cycle
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value of PC will get update the next clock cycle, and another clock cycle
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after that the instruction will get updated.
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after that the instruction will get updated.
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1- If there is data waiting on the commit bus input port this cycle,
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1- If there is data waiting on the commit bus input port this cycle,
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then do not queue this data into the FIFO but instead set
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then do not queue this data into the input FIFO but instead set
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set the score board write enable to 1, set the wSBWriteAddress
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set the score board write enable to 1, set the wSBWriteAddress
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to the CommitPacket Destination range and update the score board
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to the CommitPacket Destination range and update the score board
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bit to zero, so than in the next state the score board bit associated
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bit to zero, so than in the next state the score board bit associated
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to the commit data has been updated.
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to the commit data has been updated.
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2 - If there is no data waiting on the commit bus this clock cycle, but there
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2 - If there is no data waiting on the commit bus this clock cycle, but there
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| Line 172... |
Line 177... |
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if (wCommitBusDataAvailabe & ~wReservationStationBusy /**/& (iMtEnabled & wMtHasOnceMoreTimeSlot | ~iMtEnabled)/**/)
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if (wCommitBusDataAvailabe & ~wReservationStationBusy /**/& (iMtEnabled & wMtHasOnceMoreTimeSlot | ~iMtEnabled)/**/)
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rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
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rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
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else if (~wCommitBusInputFifo_Empty)
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else if (~wCommitBusInputFifo_Empty)
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rNextState = `II_FIFO_UPDATE;
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rNextState = `II_FIFO_UPDATE;
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else if ( wReservationStationBusy | (iMtEnabled & ~wMtHasOnceMoreTimeSlot))
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else if ( wReservationStationBusy | (iMtEnabled & ~wMtHasOnceMoreTimeSlot) /*| wIOWrite_Waiting_for_OMRead*/ )
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rNextState = `II_FETCH_INSTRUCTION;
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rNextState = `II_FETCH_INSTRUCTION;
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else
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else
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rNextState = `II_ISSUE_REQUEST;
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rNextState = `II_ISSUE_REQUEST;
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end
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end
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//--------------------------------------
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//--------------------------------------
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//TODO: If the reservation station is Busy (static hazard)
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//TODO: If the reservation station is Busy (static hazard)
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//Then we shall stall the machine...
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//Then we shall stall the machine...
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`II_ISSUE_REQUEST:
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`II_ISSUE_REQUEST:
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begin
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begin
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation;
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation_TMWRITE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rIssueNow = iEnable;
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rIssueNow = iEnable;
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rBypassFifo = 1'b0;
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rBypassFifo = 1'b0;
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| Line 209... |
Line 214... |
Here the instruction remains the same as in the
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Here the instruction remains the same as in the
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previous clock cycle.
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previous clock cycle.
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*/
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*/
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`II_ISSUE_REQUEST_WITH_DATA_FWD:
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`II_ISSUE_REQUEST_WITH_DATA_FWD:
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begin
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begin
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation;
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation_TMWRITE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rIssueNow = iEnable;
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rIssueNow = iEnable;
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rPopFifo = 1'b1;
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rPopFifo = 1'b1;
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rBypassFifo = 1'b0;
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rBypassFifo = 1'b0;
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| Line 324... |
Line 329... |
wire [SB_ENTRY_WIDTH-1:0] wSBDataPort1;
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wire [SB_ENTRY_WIDTH-1:0] wSBDataPort1;
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wire[3:0] wReservationStation;
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wire[3:0] wReservationStation;
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`ifdef ADDRESSING_MODES_DISABLED
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`ifdef ADDRESSING_MODES_DISABLED
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//There a two possible ways to update the Score board. The SB can be update by the operation we just commited: iInstruction0
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//or the SB can be updated by the value comming from the wResultFifoData
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assign wSBWriteAddress
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assign wSBWriteAddress
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= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:iInstruction0[`INST_DST_RNG])
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= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:iInstruction0[`INST_DST_RNG])
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: wResultFifoData[`COMMIT_DST_RNG];
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: wResultFifoData[`COMMIT_DST_RNG];
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`else
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`else
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//There a two possible ways to update the Score board. The SB can be update by the operation we just commited: iInstruction0
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//or the SB can be updated by the value comming from the wResultFifoData
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assign wSBWriteAddress
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assign wSBWriteAddress
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= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:wDestinationIndex)
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= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:wDestinationIndex)
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: wResultFifoData[`COMMIT_DST_RNG];
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: wResultFifoData[`COMMIT_DST_RNG];
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`endif
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`endif
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| Line 555... |
Line 563... |
assign wReservationStationBusy = (~iEnable) |
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assign wReservationStationBusy = (~iEnable) |
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(
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(
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_ADD ) && (iRStationBusy[ 0 ] && iRStationBusy[ 1 ])) ||
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_ADD ) && (iRStationBusy[ 0 ] && iRStationBusy[ 1 ])) ||
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_DIV ) && iRStationBusy[ 2 ]) ||
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_DIV ) && iRStationBusy[ 2 ]) ||
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_MUL ) && iRStationBusy[ 3 ]) ||
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_MUL ) && iRStationBusy[ 3 ]) ||
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_OUT ) && iRStationBusy[ 6 ])
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((iInstruction0[`INST_CODE_RNG] == `OPERATION_IO ) && iRStationBusy[ 6 ])
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);
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);
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assign wBranchWithDependency = (iInstruction0[`INST_BRANCH_BIT] && (wSource0_Station != 0 || wSource1_Station != 0));
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assign wBranchWithDependency = (iInstruction0[`INST_BRANCH_BIT] && (wSource0_Station != 0 || wSource1_Station != 0));
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assign wOp = iInstruction0[`INST_CODE_RNG];
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assign wOp = iInstruction0[`INST_CODE_RNG];
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//The next equations calculate the reservations stations ID based on the current operation and the availability
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//of the RS's (that is if a given statation is busy choose another suitable 1). To understand this equations
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//please refer to the table TBD in the architecture specification document
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assign wReservationStation[0] =
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assign wReservationStation[0] =
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(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 0 ]) |
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(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 0 ]) |
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(~wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 2 ]) |
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(~wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 2 ]) |
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(~wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 4 ]) |
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(~wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 4 ]) |
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| Line 603... |
Line 614... |
wire [`DATA_ADDRESS_WIDTH -1:0] wDestIndexDisplaced,wDestinationIndex_NoIMM,wDestinationIndex_IMM;
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wire [`DATA_ADDRESS_WIDTH -1:0] wDestIndexDisplaced,wDestinationIndex_NoIMM,wDestinationIndex_IMM;
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assign wDestIndexDisplaced = (iInstruction0[`INST_DST_RNG] + iFrameOffset);
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assign wDestIndexDisplaced = (iInstruction0[`INST_DST_RNG] + iFrameOffset);
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assign wDestinationIndex_NoIMM = (iInstruction0[`INST_DEST_ZERO]) ? wDestIndexDisplaced : iInstruction0[`INST_DST_RNG];
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assign wDestinationIndex_NoIMM = (iInstruction0[`INST_DEST_ZERO]) ? wDestIndexDisplaced : iInstruction0[`INST_DST_RNG];
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wire [`WIDTH-1:0 ] wSource1_X;
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assign wSource1_X = wSource1_Temp[`X_RNG];
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MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) DSTMUX
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MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) DSTMUX
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(
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(
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.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
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.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
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.I1(iInstruction0[`INST_DST_RNG]),
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.I1(iInstruction0[`INST_DST_RNG]),
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.I2(wDestIndexDisplaced),
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.I2(wDestIndexDisplaced),
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.I3(wDestIndexDisplaced),
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.I3(wDestIndexDisplaced),
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.I4(wDestIndexDisplaced + wSource1_Temp[`X_RNG]),
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.I4(wDestIndexDisplaced + wSource1_X[`DATA_ADDRESS_WIDTH-1:0]),
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.I5(iInstruction0[`INST_DST_RNG]),
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.I5(iInstruction0[`INST_DST_RNG]),
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.I6(wDestIndexDisplaced),
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.I6(wDestIndexDisplaced),
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.I7(iInstruction0[`INST_DST_RNG]),
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.I7(iInstruction0[`INST_DST_RNG]),
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.I8(wDestIndexDisplaced),
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.I8(wDestIndexDisplaced),
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.O1(wDestinationIndex_IMM)
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.O1(wDestinationIndex_IMM)
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