Subversion Repositories theia_gpu

input wire [`WB_WIDTH-1:0]           TMDAT_I,

input wire [`WB_WIDTH-1:0]           TMADR_I,

input wire                           TMWE_I,

input wire [`MAX_TMEM_BANKS-1:0]     TMSEL_I

//CROSS-BAR wires

wire [`MAX_TMEM_BANKS-1:0]                                 wTMemWriteEnable;

wire [(`MAX_TMEM_BANKS*`WB_WIDTH)-1:0]                     wCrossBarDataRow;                                     //Horizontal grid Buses comming from each bank 

wire [(`MAX_CORES*`WB_WIDTH)-1:0]                          wCrossBarDataCollumn;                                 //Vertical grid buses comming from each core.

wire [(`MAX_CORES*`WB_WIDTH)-1:0]                          wCrossBarAdressCollumn;                               //Vertical grid buses comming from each core. (physical addr).

wire [`WB_WIDTH-1:0]                                       wTMemReadAdr[`MAX_CORES-1:0];                         //Horizontal grid Buses comming from each core (virtual addr).

wire [`WB_WIDTH-1:0]                                       wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0];             //Horizontal grid Buses comming from each bank.

wire                                                       wCORE_2_TMEM__Req[`MAX_CORES-1:0];

wire [`MAX_TMEM_BANKS -1:0]                                wBankReadRequest[`MAX_CORES-1:0];

wire [`MAX_CORES-1:0]                                      wBankReadGranted[`MAX_TMEM_BANKS-1:0];

wire                                                       wTMEM_2_Core__Grant[`MAX_CORES-1:0];

wire[`MAX_CORE_BITS-1:0]                                   wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];

wire[`WIDTH-1:0]                                           wCoreBankSelect[`MAX_CORES-1:0];

                .TMEM_DAT_I( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ]    ),

      .TMEM_ADR_O( wTMemReadAdr[i]                                     ),

      .TMEM_CYC_O( wCORE_2_TMEM__Req[i]                                ),

      .TMEM_GNT_I( wTMEM_2_Core__Grant[i]                              )

        //////////////////////////////////////////////

        //

        // The OMEM

        //

        //////////////////////////////////////////////

        MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_TMEM_BANKS,`MAX_TMEM_BITS) MUXG1

                (

                .in_bus( wCrossBarDataRow ),

                .sel( wCoreBankSelect[ i ][0+:`MAX_TMEM_BITS] ),

                .out( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] )

                );

        //If there are "n" banks, memory location "X" would reside in bank number X mod n.

        //X mod 2^n == X & (2^n - 1)

        assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));

        //Each core has 1 bank request slot

        //Each slot has MAX_TMEM_BANKS bits. Only 1 bit can

        //be 1 at any given point in time. All bits zero means,

        //we are not requesting to read from any memory bank.

        SELECT_1_TO_N # ( `WIDTH, `MAX_TMEM_BANKS ) READDRQ

                        (

                        .Sel(wCoreBankSelect[ i]),

                        .En(wCORE_2_TMEM__Req[i]),

                        .O(wBankReadRequest[i])

                        );

        //The address coming from the core is  virtual adress, meaning it assumes linear

        //address space, however, since memory is interleaved in a n-way memory we transform

        //virtual adress into physical adress (relative to the bank) like this

        //fadr = vadr / n = vadr >> log2(n)

        assign wCrossBarAdressCollumn[(i*`WB_WIDTH)+:`WB_WIDTH] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);

        //Connect the granted signal to Arbiter of the Bank we want to read from  

        assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];

////////////// CROSS-BAR INTERCONECTION//////////////////////////

 SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_TMEM_BANKS ) TMWE_SEL

 (

      .Sel(TMSEL_I),

      .En(TMWE_I),

      .O(wTMemWriteEnable)

  );

genvar Core,Bank;

generate

for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)

begin : BANK

  //The memory bank itself

RAM_SINGLE_READ_PORT   # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM

  (

  .Clock(         Clock                      ),

  .iWriteEnable(  wTMemWriteEnable[Bank]       ),

  .iWriteAddress( TMADR_I                      ),

  .iDataIn(       TMDAT_I                      ),

  .iReadAddress0( wCrossBarAddressRow[Bank]    ),  //Connect to the Row of the grid

  .oDataOut0(     wCrossBarDataRow[(`WB_WIDTH*Bank)+:`WB_WIDTH]       )  //Connect to the Row of the grid

  );

  //Arbiter will Round-Robin Cores attempting to read from the same Bank

  //at a given point in time

wire [`MAX_CORES-1:0]         wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];

  Module_BusArbitrer ARB_TMEM

  (

  .Clock( Clock ),

  .Reset( Reset ),

  .iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),

  .oGrant(   wBankReadGrantedDelay[Bank]  ),     //The bit of the core granted to read from this Bank

  .oBusSelect( wCurrentCoreSelected[Bank] )      //The index of the core granted to read from this Bank

  );

  FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT

(

  .Clock(Clock),

  .Reset(Reset),

  .Enable( 1'b1 ),

  .D(wBankReadGrantedDelay[Bank]),

  .Q(wBankReadGranted[Bank])

);

 MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_CORES,`MAX_CORE_BITS) MUXG2

        (

        .in_bus( wCrossBarAdressCollumn ),

        .sel( wCurrentCoreSelected[ Bank ] ),

        .out( wCrossBarAddressRow[ Bank ] )

        );

end

endgenerate

////////////// CROSS-BAR INTERCONECTION//////////////////////////