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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Unit_ControlProcessor.v] - Diff between revs 213 and 230

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Rev 213 Rev 230
Line 19... Line 19...
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
 
***********************************************************************************/
***********************************************************************************/
 
 
 
 
`define CONTROL_PROCESSOR_OP_WIDTH            5
 
`define CONTROL_PROCESSOR_ADDR_WIDTH          8
`define CONTROL_PROCESSOR_ADDR_WIDTH          8
`define CONTROL_PROCESSOR_ISSUE_CMD_RNG       24:0
`define CONTROL_PROCESSOR_ISSUE_CMD_RNG       24:0
`define CONTROL_PROCESSOR_INSTRUCTION_WIDTH   32
`define CONTROL_PROCESSOR_INSTRUCTION_WIDTH   32
 
 
`define CONTROL_PROCESSOR_INST_OP_RNG         31:24
`define CONTROL_PROCESSOR_INST_OP_RNG         31:24
Line 69... Line 69...
reg  [`CBC_BUS_WIDTH-1:0]                                    rIssueCommand;
reg  [`CBC_BUS_WIDTH-1:0]                                    rIssueCommand;
wire [`CONTROL_PROCESSOR_INSTRUCTION_WIDTH-1:0]              wInstruction;
wire [`CONTROL_PROCESSOR_INSTRUCTION_WIDTH-1:0]              wInstruction;
wire [`CONTROL_PROCESSOR_OP_WIDTH-1:0]                       wOperation;
wire [`CONTROL_PROCESSOR_OP_WIDTH-1:0]                       wOperation;
reg  [`WIDTH-1:0]                                            rResult;
reg  [`WIDTH-1:0]                                            rResult;
wire [`WIDTH-1:0]                                            wPrevResult;
wire [`WIDTH-1:0]                                            wPrevResult;
wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0]                     wSourceAddr0,wSourceAddr1,wDestination,wPrevDestination;
wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0]                     wSourceAddr0,wSourceAddr1,wDestination,wPrevDestination,wIPInitialValue;
wire [`WIDTH-1:0]                                            wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
wire [`WIDTH-1:0]                                            wSourceData0,wSourceData1,wImmediateValue;
 
 
 
 
assign oControlBus = rIssueCommand;
assign oControlBus = rIssueCommand;
 
 
RAM_SINGLE_READ_PORT # (`CONTROL_PROCESSOR_INSTRUCTION_WIDTH, `CONTROL_PROCESSOR_ADDR_WIDTH, 256) InstructionRam
RAM_SINGLE_READ_PORT # (`CONTROL_PROCESSOR_INSTRUCTION_WIDTH, `CONTROL_PROCESSOR_ADDR_WIDTH, 256) InstructionRam
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assign wIPInitialValue = (Reset) ? `CONTROL_PROCESSOR_ADDR_WIDTH'b0 : wDestination;
assign wIPInitialValue = (Reset) ? `CONTROL_PROCESSOR_ADDR_WIDTH'b0 : wDestination;
UPCOUNTER_POSEDGE # (`CONTROL_PROCESSOR_ADDR_WIDTH) IP
UPCOUNTER_POSEDGE # (`CONTROL_PROCESSOR_ADDR_WIDTH) IP
(
(
.Clock(   Clock                ),
.Clock(   Clock                ),
.Reset(   Reset | rBranchTaken ),
.Reset(   Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1  ),
.Initial( wIPInitialValue + `CONTROL_PROCESSOR_ADDR_WIDTH'd1  ),
.Enable(  1'b1                 ),
.Enable(  1'b1                 ),
.Q(       wIP_temp             )
.Q(       wIP_temp             )
);
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
 
 

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