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https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`define MAIN_MEMORY_DEPTH (255 * 2) //Each entry is 64 bits = 32 *2 * 255 entries
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module testbench_theia_icarus;
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module testbench_theia_icarus;
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reg Clock;
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reg Clock;
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reg Reset;
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reg Reset;
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VectorProcessor_Dumper #(0) VP_Dump0();
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VectorProcessor_Dumper #(0) VP_Dump0();
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VectorProcessor_Dumper #(1) VP_Dump1();
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VectorProcessor_Dumper #(1) VP_Dump1();
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VectorProcessor_Dumper #(2) VP_Dump2();
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VectorProcessor_Dumper #(2) VP_Dump2();
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VectorProcessor_Dumper #(3) VP_Dump3();
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VectorProcessor_Dumper #(3) VP_Dump3();
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reg [31:0] MainMemory [255:0];
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reg [31:0] InstMemory [31:0];
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reg [31:0] MainMemory [`MAIN_MEMORY_DEPTH-1:0];
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always @ (posedge Clock )
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always @ (posedge Clock )
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begin
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begin
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if (oMEM_ReadRequest)
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if (oMEM_ReadRequest)
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iMemReadData <= MainMemory[oMemReadAddress];
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iMemReadData <= MainMemory[oMemReadAddress];
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end
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end
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initial begin
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initial begin
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Clock = 0;
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Clock = 0;
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Reset = 0;
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Reset = 0;
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iEnable = 0;
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iEnable = 0;
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$readmemh("control_code.mem", uut.CP.InstructionRam.Ram);
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$readmemh("control_code.mem", uut.CP.InstructionRam.Ram);
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$readmemh("code.mem", MainMemory);
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$readmemh("code.mem", MainMemory);
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#110;
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#110;
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Reset = 1;
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Reset = 1;
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#40;
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#40;
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Reset = 0;
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Reset = 0;
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$dumpfile("dump.vcd");
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$dumpvars(0,testbench_theia_icarus);
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end
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end
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endmodule
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endmodule
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