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Line 26... |
all over the code. By now you have may noticed that all
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all over the code. By now you have may noticed that all
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constants are pre-compilation define directives. This is
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constants are pre-compilation define directives. This is
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for simulation perfomance reasons mainly.
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for simulation perfomance reasons mainly.
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*******************************************************************************/
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*******************************************************************************/
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`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
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`define MAX_CORES 16 //The number of cores, make sure you update MAX_CORE_BITS!
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`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
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`define MAX_CORE_BITS 4 // 2 ^ MAX_CORE_BITS = MAX_CORES
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`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
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`define MAX_TMEM_BANKS 16 //The number of memory banks for TMEM
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`define SELECT_ALL_CORES `MAX_CORES'b1111111111111111 //XXX: Change for more cores
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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//Verilog provides a `default_nettype none compiler directive. When
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//Verilog provides a `default_nettype none compiler directive. When
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//this directive is set, implicit data types are disabled, which will make any
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//this directive is set, implicit data types are disabled, which will make any
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//undeclared signal name a syntax error.This is very usefull to avoid annoying
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//undeclared signal name a syntax error.This is very usefull to avoid annoying
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//automatic 1 bit long wire declaration where you don't want them to be!
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//automatic 1 bit long wire declaration where you don't want them to be!
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Line 367... |
`define SWIZZLE_ZYZ 32'd20
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`define SWIZZLE_ZYZ 32'd20
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`define SWIZZLE_YXZ 32'd21
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`define SWIZZLE_YXZ 32'd21
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No newline at end of file
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No newline at end of file
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No newline at end of file
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No newline at end of file
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