| Line 10... |
Line 10... |
//Theia Interfaces
|
//Theia Interfaces
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input wire MST_I, //Master signal, THEIA enters configuration mode
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input wire MST_I, //Master signal, THEIA enters configuration mode
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//when this gets asserted (see documentation)
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//when this gets asserted (see documentation)
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//Wish Bone Interface
|
//Wish Bone Interface
|
input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
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//output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
|
input wire ACK_I, //Input ack
|
input wire ACK_I, //Input ack
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output wire ACK_O, //Output ack
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output wire ACK_O, //Output ack
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output wire [`WB_WIDTH-1:0] ADR_O, //Output address
|
//output wire [`WB_WIDTH-1:0] ADR_O, //Output address
|
input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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output wire WE_O, //Output write enable
|
//output wire WE_O, //Output write enable
|
input wire WE_I, //Input write enable
|
input wire WE_I, //Input write enable
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output wire STB_O, //Strobe signal, see wishbone documentation
|
//output wire STB_O, //Strobe signal, see wishbone documentation
|
input wire STB_I, //Strobe signal, see wishbone documentation
|
input wire STB_I, //Strobe signal, see wishbone documentation
|
output wire CYC_O, //Bus cycle signal, see wishbone documentation
|
//output wire CYC_O, //Bus cycle signal, see wishbone documentation
|
input wire CYC_I, //Bus cycle signal, see wishbone documentation
|
input wire CYC_I, //Bus cycle signal, see wishbone documentation
|
output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
|
//output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
|
input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
|
input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
|
output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
|
//output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
|
input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
|
//input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
|
input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
|
input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
|
input wire [`MAX_CORES-1:0] RENDREN_I,
|
input wire [`MAX_CORES-1:0] RENDREN_I,
|
|
|
|
input wire [`MAX_CORE_BITS-1:0] OMBSEL_I, //Output memory bank select
|
|
input wire [`WB_WIDTH-1:0] OMADR_I, //Output adress (relative to current bank)
|
|
output wire [`WB_WIDTH-1:0] OMEM_O, //Output data bus (Wishbone)
|
|
|
|
input wire [`WB_WIDTH-1:0] TMDAT_I,
|
|
input wire [`WB_WIDTH-1:0] TMADR_I,
|
|
input wire TMWE_I,
|
|
input wire [`MAX_TMEM_BANKS-1:0] TMSEL_I,
|
//Control Register
|
//Control Register
|
input wire [15:0] CREG_I,
|
input wire [15:0] CREG_I,
|
|
output wire GRDY_O,
|
|
input wire STDONE_I,
|
|
input wire HDA_I,
|
|
input wire GACK_I,
|
|
output wire RCOMMIT_O,
|
output wire DONE_O
|
output wire DONE_O
|
|
|
);
|
);
|
|
|
|
|
|
|
|
|
|
wire [`MAX_TMEM_BANKS-1:0] wTMemWriteEnable;
|
|
SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_TMEM_BANKS ) TMWE_SEL
|
|
(
|
|
.Sel(TMSEL_I),
|
|
.En(TMWE_I),
|
|
.O(wTMemWriteEnable)
|
|
);
|
|
|
|
|
wire [`MAX_CORES-1:0] wDone;
|
wire [`MAX_CORES-1:0] wDone;
|
wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
|
wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
|
wire [`WB_WIDTH-1:0] wDAT_O_0,wDAT_O_1,wDAT_O_2,wDAT_O_3;
|
//wire [`WB_WIDTH-1:0] wDAT_O[`MAX_CORES-1:0];
|
wire [`WB_WIDTH-1:0] wADR_O_0,wADR_O_1,wADR_O_2,wADR_O_3;
|
//wire [`WB_WIDTH-1:0] wADR_O[`MAX_CORES-1:0];
|
wire [1:0] wTGA_O_0,wTGA_O_1,wTGA_O_2,wTGA_O_3;
|
//wire [1:0] wTGA_O[`MAX_CORES-1:0];
|
wire [1:0] wBusSelect;
|
wire [`MAX_CORE_BITS-1:0] wBusSelect;
|
|
|
|
|
//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
|
//wire [`MAX_CORES-1:0] wSTB_O;
|
//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
|
//wire [`MAX_CORES-1:0] wWE_O;
|
|
wire [`MAX_CORES-1:0]wACK_O;
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|
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wire [`MAX_CORES-1:0] wSTB_O,wWE_O,wACK_O;
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|
|
|
|
wire wOMem_WE[`MAX_CORES-1:0];
|
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wire [`WB_WIDTH-1:0] wOMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
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|
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wire [`MAX_CORES-1:0] wSTB_I;
|
wire [`MAX_CORES-1:0] wSTB_I;
|
wire [`MAX_CORES-1:0] wMST_I;
|
wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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|
|
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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|
//assign DONE_O = wDone[0];
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//assign DONE_O = wDone[0] & wDone[1];// & wDone[2];
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|
//----------------------------------------------------------------
|
//wire [`MAX_CORES-1:0] wTMEM_ACK_I;
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// assign wDone[3:1] = 3'b111;
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wire [`WB_WIDTH-1:0] wTMEM_Data;
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// assign wBusRequest[3:2] = 0;
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wire [`WB_WIDTH-1:0] wTMEM_Address[`MAX_CORES-1:0];
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// assign wSTB_O[3:2] = 0;
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wire [`WB_WIDTH-1:0] wTMEM_ReadAddr;
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// assign wWE_O[3:2] = 0;
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//wire [`MAX_CORES-1:0] wTMEM_STB_O;
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Module_BusArbitrer ARB1
|
wire [`MAX_CORES-1:0] wTMEM_Resquest;
|
(
|
wire [`MAX_CORES-1:0] wTMEM_Granted;
|
.Clock( CLK_I ),
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.Reset( RST_I ),
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.iRequest( wBusRequest ),
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.oGrant( wBusGranted ),
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|
.oBusSelect( wBusSelect )
|
|
|
|
);
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|
//----------------------------------------------------------------
|
|
//The Muxes
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//DAT_O Mux
|
|
MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_DAT_O
|
|
(
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|
.Sel(wBusSelect),
|
|
.I1(wDAT_O_0),
|
|
.I2(wDAT_O_1),
|
|
.I3(wDAT_O_2),
|
|
.I4(wDAT_O_3),
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|
.O1( DAT_O )
|
|
);
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_ADR_O
|
|
(
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.Sel(wBusSelect),
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.I1(wADR_O_0),
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.I2(wADR_O_1),
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.I3(wADR_O_2),
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|
.I4(wADR_O_3),
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.O1( ADR_O )
|
|
);
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//CROSS-BAR cables
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_STB_O
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|
(
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.Sel(wBusSelect),
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.I1(wSTB_O[0]),
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.I2(wSTB_O[1]),
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.I3(wSTB_O[2]),
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.I4(wSTB_O[3]),
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.O1( STB_O )
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|
);
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wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank
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wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core.
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_WE_O
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
|
(
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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.Sel(wBusSelect),
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.I1(wWE_O[0]),
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.I2(wWE_O[1]),
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.I3(wWE_O[2]),
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.I4(wWE_O[3]),
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.O1( WE_O )
|
|
);
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MUXFULLPARALELL_2SEL_GENERIC # ( 2 ) MUX_TGA_O
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
|
(
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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.Sel(wBusSelect),
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.I1(wTGA_O_0),
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.I2(wTGA_O_1),
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.I3(wTGA_O_2),
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.I4(wTGA_O_3),
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.O1( TGA_O )
|
|
);
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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//wire [`WB_WIDTH-1:0] wTMEM_2_Core_Data[`MAX_CORES-1:0]; //Vertical grid Buses going to each core.
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wire[7:0] wCoreBankSelect[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wGRDY_O;
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assign ACK_O = (wACK_O[0] | wACK_O[1] | wACK_O[2] | wACK_O[3]);
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assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
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assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
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assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
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assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
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assign wSTB_I[0] = (SEL_I[0]) ? STB_I : 0;
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assign wSTB_I[1] = (SEL_I[1]) ? STB_I : 0;
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assign wSTB_I[2] = (SEL_I[2]) ? STB_I : 0;
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assign wSTB_I[3] = (SEL_I[3]) ? STB_I : 0;
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assign wCYC_I[0] = (SEL_I[0]) ? CYC_I : 0;
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assign wCYC_I[1] = (SEL_I[1]) ? CYC_I : 0;
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assign wCYC_I[2] = (SEL_I[2]) ? CYC_I : 0;
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assign wCYC_I[3] = (SEL_I[3]) ? CYC_I : 0;
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assign wTGA_I[0] = (SEL_I[0]) ? TGA_I : 0;
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assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
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assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
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assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
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|
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//----------------------------------------------------------------
|
wire [`MAX_CORES-1:0] wGReady;
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wire [`MAX_CORES-1:0] wRCOMMIT_O;
|
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wire [`MAX_CORES-1:0] wRCommited;
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|
THEIACORE THEIA_CORE0
|
|
(
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|
.CLK_I( CLK_I ),
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.RST_I( RST_I ),
|
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.RENDREN_I( RENDREN_I[0] ),
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|
|
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//Slave signals
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assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
|
.ADR_I( ADR_I ),
|
assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3];
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.WE_I( WE_I ),
|
//----------------------------------------------------------------
|
.STB_I( wSTB_I[0] ),
|
//The next secuencial logic just AND all the wDone signals
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//-----------------------------------
|
//I know that it would be much more elgant to just do parallel:
|
//This signal behaves in a very funny way...
|
//assign DONE_O = wDone[0] & wDone[1] & ... & wDone[MAX_CORES-1];
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//
|
//However, I don't know how to achieve this with 'generate' statements
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.ACK_I( ACK_I ),
|
//So coding a simple loop instead
|
//-----------------------------------
|
|
.CYC_I( wCYC_I[0] ),
|
/*
|
.MST_I( wMST_I[0] ),
|
always @ (posedge CLK_I)
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.TGA_I( wTGA_I[0] ),
|
begin : AND_DONE_SIGNALS
|
.CREG_I( CREG_I ),
|
integer k;
|
|
DONE_O = wDone[0];
|
|
for (k=0;k<=`MAX_CORES;k=k+1)
|
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DONE_O=DONE_O & wDone[k+1];
|
|
end
|
|
*/
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3]; //Replace this by a counter??
|
|
//----------------------------------------------------------------
|
|
|
//Master Signals
|
Module_BusArbitrer ARB1
|
.WE_O ( wWE_O[0] ),
|
(
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.STB_O( wSTB_O[0] ),
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.Clock( CLK_I ),
|
.ACK_O( wACK_O[0] ),
|
.Reset( RST_I ),
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.DAT_O( wDAT_O_0 ),
|
.iRequest( wBusRequest ),
|
.ADR_O( wADR_O_0 ),
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.oGrant( wBusGranted ),
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.CYC_O( wBusRequest[0] ),
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.oBusSelect( wBusSelect )
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.GNT_I( wBusGranted[0] ),
|
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.TGA_O( wTGA_O_0 ),
|
|
`ifdef DEBUG
|
|
.iDebug_CoreID( `MAX_CORES'd0 ),
|
|
`endif
|
|
//Other
|
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.DAT_I( DAT_I ),
|
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.DONE_O( wDone[0] )
|
|
|
|
);
|
);
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
THEIACORE THEIA_CORE1
|
|
|
// assign DAT_O = wDAT_O[ wBusSelect ];
|
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// assign TGA_O = wTGA_O[ wBusSelect ];
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// assign ADR_O = wADR_O[ wBusSelect ];
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// assign STB_O = wSTB_O[ wBusSelect ];
|
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// assign WE_O = wWE_O[ wBusSelect ];
|
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assign ACK_O = wACK_O[ wBusSelect];
|
|
|
|
wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0];
|
|
assign OMEM_O = wDataOut[ OMBSEL_I ];
|
|
|
|
genvar i;
|
|
generate
|
|
for (i = 0; i < `MAX_CORES; i = i +1)
|
|
begin : CORE
|
|
assign wMST_I[i] = (SEL_I[i]) ? MST_I : 0;
|
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assign wSTB_I[i] = (SEL_I[i]) ? STB_I : 0;
|
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assign wCYC_I[i] = (SEL_I[i]) ? CYC_I : 0;
|
|
assign wTGA_I[i] = (SEL_I[i]) ? TGA_I : 0;
|
|
|
|
|
|
THEIACORE CTHEIA
|
(
|
(
|
.CLK_I( CLK_I ),
|
.CLK_I( CLK_I ),
|
.RST_I( RST_I ),
|
.RST_I( RST_I ),
|
.RENDREN_I( RENDREN_I[1] ),
|
.RENDREN_I( RENDREN_I[i] ),
|
|
|
//Slave signals
|
//Slave signals
|
.ADR_I( ADR_I ),
|
.ADR_I( ADR_I ),
|
.WE_I( WE_I ),
|
.WE_I( WE_I ),
|
.STB_I( wSTB_I[1] ),//ok
|
.STB_I( wSTB_I[i] ),
|
.ACK_I( ACK_I ),
|
.ACK_I( ACK_I ),
|
.CYC_I( wCYC_I[1] ),//ok
|
.CYC_I( wCYC_I[i] ),
|
.MST_I( wMST_I[1] ),//ok
|
.MST_I( wMST_I[i] ),
|
.TGA_I( wTGA_I[1] ),//ok
|
.TGA_I( wTGA_I[i] ),
|
.CREG_I( CREG_I ),
|
.CREG_I( CREG_I ),
|
|
|
//Master Signals
|
//Master Signals
|
.WE_O ( wWE_O[1] ),
|
//.WE_O ( wWE_O[i] ),
|
.STB_O( wSTB_O[1] ),
|
//.STB_O( wSTB_O[i] ),
|
.ACK_O( wACK_O[1] ),
|
.ACK_O( wACK_O[i] ),
|
.DAT_O( wDAT_O_1 ),
|
// .DAT_O( wDAT_O[i] ),
|
.ADR_O( wADR_O_1 ),
|
//.ADR_O( wADR_O[i] ),
|
.CYC_O( wBusRequest[1] ),
|
.CYC_O( wBusRequest[i] ),
|
.GNT_I( wBusGranted[1] ),
|
.GNT_I( wBusGranted[i] ),
|
.TGA_O( wTGA_O_1 ),
|
//.TGA_O( wTGA_O[i] ),
|
`ifdef DEBUG
|
`ifdef DEBUG
|
.iDebug_CoreID( `MAX_CORES'd1 ),
|
.iDebug_CoreID( i ),
|
`endif
|
`endif
|
|
|
|
.OMEM_WE_O( wOMem_WE[i] ),
|
|
.OMEM_ADR_O( wOMEM_Address[i] ),
|
|
.OMEM_DAT_O( wOMEM_Dat[i] ),
|
|
|
|
|
|
|
|
.TMEM_DAT_I( wCrossBarDataCollumn[i] ),
|
|
.TMEM_ADR_O( wTMemReadAdr[i] ),
|
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
|
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ),
|
|
|
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.GRDY_O( wGRDY_O[i] ),
|
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.STDONE_I( STDONE_I ),
|
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.RCOMMIT_O( wRCOMMIT_O[i] ),
|
|
.HDA_I( HDA_I ),
|
|
|
//Other
|
//Other
|
.DAT_I( DAT_I ),
|
.DAT_I( DAT_I ),
|
.DONE_O( wDone[1] )
|
.DONE_O( wDone[i] )
|
|
|
);
|
);
|
//----------------------------------------------------------------
|
|
THEIACORE THEIA_CORE2
|
UPCOUNTER_POSEDGE # (1) UP_RCOMMIT
|
(
|
(
|
.CLK_I( CLK_I ),
|
.Clock( CLK_I ),
|
.RST_I( RST_I ),
|
.Reset( RST_I | GACK_I ),
|
.RENDREN_I( RENDREN_I[2] ),
|
.Initial( 1'b0 ),
|
|
.Enable( wRCOMMIT_O[i] ),
|
|
.Q(wRCommited[i])
|
|
);
|
|
|
//Slave signals
|
UPCOUNTER_POSEDGE # (1) UP_GREADY
|
.ADR_I( ADR_I ),
|
(
|
.WE_I( WE_I ),
|
.Clock( CLK_I ),
|
.STB_I( wSTB_I[2] ),
|
.Reset( RST_I | GACK_I ),
|
.ACK_I( ACK_I ),
|
.Initial( 1'b0 ),
|
.CYC_I( wCYC_I[2] ),
|
.Enable( wGRDY_O[i] ),
|
.MST_I( wMST_I[2] ),
|
.Q(wGReady[i])
|
.TGA_I( wTGA_I[2] ),
|
);
|
.CREG_I( CREG_I ),
|
|
|
|
//Master Signals
|
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 500000 ) OMEM //10k mem
|
.WE_O ( wWE_O[2] ),
|
(
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.STB_O( wSTB_O[2] ),
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.Clock( CLK_I ),
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.ACK_O( wACK_O[2] ),
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.iWriteEnable( wOMem_WE[i] ),
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.DAT_O( wDAT_O_2 ),
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.iWriteAddress( wOMEM_Address[i] ),
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.ADR_O( wADR_O_2 ),
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.iDataIn( wOMEM_Dat[i] ),
|
.CYC_O( wBusRequest[2] ),
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.iReadAddress0( OMADR_I ),
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.GNT_I( wBusGranted[2] ),
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.oDataOut0( wDataOut[i] )
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.TGA_O( wTGA_O_2 ),
|
|
`ifdef DEBUG
|
|
.iDebug_CoreID( `MAX_CORES'd2 ),
|
|
`endif
|
|
//Other
|
|
.DAT_I( DAT_I ),
|
|
.DONE_O( wDone[2] )
|
|
|
|
);
|
);
|
//----------------------------------------------------------------
|
|
THEIACORE THEIA_CORE3
|
|
|
//If there are "n" banks, memory location "X" would reside in bank number X mod n.
|
|
//X mod 2^n == X & (2^n - 1)
|
|
assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));
|
|
|
|
//Each core has 1 bank request slot
|
|
//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
|
|
//be 1 at any given point in time. All bits zero means,
|
|
//we are not requesting to read from any memory bank.
|
|
SELECT_1_TO_N # ( 8, 4 ) READDRQ
|
(
|
(
|
.CLK_I( CLK_I ),
|
.Sel(wCoreBankSelect[ i]),
|
.RST_I( RST_I ),
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.En(wCORE_2_TMEM__Req[i]),
|
.RENDREN_I( RENDREN_I[3] ),
|
.O(wBankReadRequest[i])
|
|
);
|
|
|
//Slave signals
|
//The address coming from the core is virtual adress, meaning it assumes linear
|
.ADR_I( ADR_I ),
|
//address space, however, since memory is interleaved in a n-way memory we transform
|
.WE_I( WE_I ),
|
//virtual adress into physical adress (relative to the bank) like this
|
.STB_I( wSTB_I[3] ),
|
//fadr = vadr / n = vadr >> log2(n)
|
.ACK_I( ACK_I ),
|
|
.CYC_I( wCYC_I[3] ),
|
|
.MST_I( wMST_I[3] ),
|
|
.TGA_I( wTGA_I[3] ),
|
|
.CREG_I( CREG_I ),
|
|
|
|
//Master Signals
|
assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> ((`MAX_TMEM_BANKS)/2));
|
.WE_O ( wWE_O[3] ),
|
|
.STB_O( wSTB_O[3] ),
|
//Connect the granted signal to Arbiter of the Bank we want to read from
|
.ACK_O( wACK_O[3] ),
|
assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
|
.DAT_O( wDAT_O_3 ),
|
|
.ADR_O( wADR_O_3 ),
|
//Connect the request signal to Arbiter of the Bank we want to read from
|
.CYC_O( wBusRequest[3] ),
|
//assign wBankReadRequest[wCoreBankSelect[i]][i] = wCORE_2_TMEM__Req[i];
|
.GNT_I( wBusGranted[3] ),
|
|
.TGA_O( wTGA_O_3 ),
|
end
|
`ifdef DEBUG
|
endgenerate
|
.iDebug_CoreID( `MAX_CORES'd3 ),
|
|
`endif
|
|
//Other
|
////////////// CROSS-BAR INTERCONECTION//////////////////////////
|
.DAT_I( DAT_I ),
|
|
.DONE_O( wDone[3] )
|
genvar Core,Bank;
|
|
generate
|
|
for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)
|
|
begin : BANK
|
|
|
|
//The memory bank itself
|
|
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM
|
|
(
|
|
.Clock( CLK_I ),
|
|
.iWriteEnable( wTMemWriteEnable[Bank] ),
|
|
.iWriteAddress( TMADR_I ),
|
|
.iDataIn( TMDAT_I ),
|
|
.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid
|
|
.oDataOut0( wCrossBarDataRow[Bank] ) //Connect to the Row of the grid
|
|
|
|
);
|
|
|
|
//Arbiter will Round-Robin Cores attempting to read from the same Bank
|
|
//at a given point in time
|
|
wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];
|
|
Module_BusArbitrer ARB_TMEM
|
|
(
|
|
.Clock( CLK_I ),
|
|
.Reset( RST_I ),
|
|
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),//wBankReadRequest[Bank] ), //The cores requesting to read from this Bank
|
|
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
|
|
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
|
|
|
);
|
);
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT
|
|
(
|
|
.Clock(CLK_I),
|
|
.Reset(RST_I),
|
|
.Enable( 1'b1 ),
|
|
.D(wBankReadGrantedDelay[Bank]),
|
|
.Q(wBankReadGranted[Bank])
|
|
);
|
|
|
|
|
|
//Create the Cross-Bar interconnection grid now, rows are coonected to the memory banks,
|
|
//while collumns are connected to the cores, 2 or more cores can not read from the same
|
|
//bank at any given point in time
|
|
for (Core = 0; Core < `MAX_CORES; Core = Core + 1)
|
|
begin: CORE_CONNECT
|
|
//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank
|
|
assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz;
|
|
//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading
|
|
assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz;
|
|
|
|
end
|
|
|
|
end
|
|
endgenerate
|
|
|
|
////////////// CROSS-BAR INTERCONECTION//////////////////////////
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
|
|
endmodule
|
endmodule
|
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
